Commissariat a L'energie Atomique

Soitec

S.o.i.tec Silicon on Insulator Technologies

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Commissariat À L'energie Atomique (cea)

Tracit Technologies

E2v Semiconductors

Commissariat a L'atomique

S.o.i. Tec Silicon on Insulator Technologies of Chemin Des Franques

Bernard Aspar

Michel Bruel

Hubert Moriceau

Olivier Rayssac

Christophe Maleville

Chrystelle Lagahe Blanchard

Marc Zussy

Chrystelle Lagahe-Blanchard

Thierry Poumeyrol

Chrystelle Lagahe

Ionut Radu

Thierry Barge

Daniel Delprat

Arnaud Castex

Eric Jalaguier

Bruno Ghyselen

Fabrice Letertre

Mariam G Sadaka

Eric Desbonnets

Jean-Frédéric Clerc

Nicolas Sousbie

Franck Fournel

Christophe Figuet

Claude Jaussaud

Jacques Margail

Séverine Bressot

Frank Fournel

Marcel Broekaart

Jean-Pierre Joly

Alexis Drouin

Philippe Rommeveaux

Beatrice Biasse

Jean-Yves Robic

Gilles Poupon

François Baleras

Olivier Ledoux

Christelle Lagahe

Philippe Montmayeul

Aurélie Beaumont

Christophe Desrumaux

Chrystelle Lagache

Vincent Blet

Anne-Marie Cartier

Andr&eacute;-Jacques Auberton-Herve

B&eacute;atrice Biasse

Catherine Pudda

André-Jacques Auberton-Herve

Jean-François Michaud

A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.

Structure for radio frequency applications

The present invention relates to a heterostructure, in particular, a piezoelectric structure, comprising a cover layer, in particular, a layer of piezoelectric material, the material of the cover layer having a first coefficient of thermal expansion, assembled to a support substrate, the support substrate having a second coefficient of thermal expansion substantially different from the first coefficient of thermal expansion, at an interface wherein the cover layer comprises at least a recess extending from the interface into the cover layer, and its method of fabrication.

Heterostructure and method of fabrication

Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.

Methods for fabrication of semiconductor structures using laser lift-off process, and related semiconductor structures

Methods are used to form semiconductor devices that include an integrated circuit and a microelectromechanical system (MEMS) device operatively coupled with the integrated circuit. At least a portion of an integrated circuit may be fabricated on a surface of a substrate, and a MEMS device may be formed over the at least a portion of the integrated circuit. The MEMS device may be operatively coupled with the integrated circuit. Semiconductor structures and electronic devices including such structures are formed using such methods.

Methods of forming semiconductor structures including MEMS devices and integrated circuits on common sides of substrates, and related structures and devices

Methods of forming semiconductor devices comprising integrated circuits and microelectromechanical system (MEMS) devices operatively coupled with the integrated circuits involve the formation of an electrically conductive via extending at least partially through a substrate from a first major surface of the substrate toward an opposing second major surface of the substrate, and the fabrication of at least a portion of an integrated circuit on the first major surface of the substrate. A MEMS device is provided on the second major surface of the substrate, and the MEMS device is operatively coupled with the integrated circuit using the at least one electrically conductive via. Structures and devices are fabricated using such methods.

Methods of forming semiconductor structures including MEMS devices and integrated circuits on opposing sides of substrates, and related structures and devices

The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.

Process of treating defects during the bonding of wafers

A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.

Manufacturing process for a stacked structure comprising a thin layer bonding to a target substrate

A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.

Method for trimming a structure obtained by the assembly of two plates

A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.

Process for the transfer of a thin film comprising an inclusion creation step

The invention relates to a method for fabricating a semiconductor substrate by providing a silicon on insulator type substrate that includes a base, an insulating layer and a first semiconductor layer, doping the first semiconductor layer to thereby obtain a modified first semiconductor layer, and providing a second semiconductor layer with a different dopant concentration than the modified first semiconductor layer over or on the modified first semiconductor layer. With this method, an improved dopant concentration profile can be achieved through the various layers which makes the substrates in particular more suitable for various optoelectronic applications.

Method for fabricating a semiconductor substrate

Growing community of inventors

Rives, France

Bernard Aspar