Samsung Electronics Co., Ltd.

Beom-jun Jin

Sang-Guk Han

Seok-Joon Moon

Byung-seo Kim

Young-pil Kim

Byeong-yun Nam

Sung-Dong Kim

Young-Pil Kim

Byeong-Yun Nam

Hyoung-Joon Kim

Young-sun Kim

Yu-Gyun Shin

Sang-Bom Kang

Hong-bae Park

Jin-Jun Park

Hye-Lan Lee

Eun-ae Chung

U-in Chung

Taek-Soo Jeon

Hag-Ju Cho

Ki-hyun Hwang

Seong-Geon Park

Jung-Hwan Oh

Hee-Seok Kim

Seok-woo Nam

Won-sik Shin

Hyo-jung Kim

Hee-Jin Kwak

An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

Circuit board having bypass pad

A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.

Methods of forming non-volatile memory devices including vertical NAND strings

Non-volatile memory devices including vertical NAND strings and methods of forming the same

Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate.

Non-volatile semiconductor memory device and method of manufacturing the same

A method of forming transistor gate structures in an integrated circuit device can include forming a high-k gate insulating layer on a substrate including a first region to include PMOS transistors and a second region to include NMOS transistors. A polysilicon gate layer can be formed on the high-k gate insulating layer in the first and second regions. A metal silicide gate layer can be formed directly on the high-k gate insulating layer in the first region and avoiding forming the metal-silicide in the second region. Related gate structures are also disclosed.

Methods of forming different gate structures in NMOS and PMOS regions and gate structures so formed

Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.

Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors

A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySiGelayer stacked on the metallic layer. Methods of forming these capacitors also are provided.

Methods of forming capacitors of semiconductor devices including silicon-germanium and metallic electrodes

A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask layers at sidewalls of gate electrodes in a cell area. Also, an interlevel dielectric layer is formed of a material having an excellent etching selectivity to the etch mask layers. The sacrificial spacers are removed when forming the self-aligned contact holes. Dielectric spacers are formed of a material having a low dielectric constant, without considering its etching selectivity to the interlevel dielectric layer. Thus, a reduction in the operational speed of a semiconductor device having transistors can be prevented.

Semiconductor device having transistor and method of manufacturing the same

An integrated circuit device includes a substrate that has a source region and a drain region formed therein. A gate pattern is disposed on the substrate between the source region and the drain region. A lower pad layer is disposed on the source region and/or the drain region and comprises a same crystalline structure as the substrate. A conductive layer is disposed on the lower pad layer such that at least a portion of the conductive layer is disposed between the lower pad layer and the gate pattern. An insulating layer is disposed between the gate pattern and both the lower pad layer and the conductive layer, and also between the conductive layer and the substrate.

Methods of manufacturing integrated circuit devices having reduced contact resistance between a substrate and a contact pad while maintaining separation of the substrate and the contact pad and integrated circuit devices formed thereby

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Seoul, South Korea

Beom-jun Jin