Freescale Semiconductor,inc.

Bennett Joiner

Yaping Zhou

Yuan Yuan

Mark Allen Gerber

Trent A Thompson

Ben W Herberg

Chuchung (Stephen) Lee

Jose Antonio Montes De Oca

An integrated circuit package () is provided which comprises a substrate (), an integrated circuit () mounted on the substrate, and a compressive, thermally conductive interposer () mounted on the integrated circuit.

Thermally enhanced molded package for semiconductors

A semiconductor device has a die () overlying and electrically connected to a support structure (), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects () are noise sources to victim interconnects () carrying sensitive signals. An arrangement of shield interconnects () surround the victim interconnect () in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.

Electromagnetic noise shielding in semiconductor packages using caged interconnect structures

A package substrate () has a first surface, a second surface opposite a first surface, and a cavity () formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die () is placed in the cavity, and a conductive material () is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer () may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Low profile semiconductor device having improved heat dissipation

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Austin, TX, United States of America

Bennett Joiner