United Microelectronics Corp.

Infineon Technologies Ag

Winbond Electronics Corporation

Other

United Microelectronics Co.

Benjamin Szu-Min Lin

Chuan-Fu Wang

Sebastian Schmidt

Hang Yip Liu

Jason Jyh-shyang Jenq

George Liu

Chun-Chi Yu

Jung-Chao Chiou

Hui-Ling Huang

Cheng-Chung Chen

Jhy-Jyi Sze

Ming-Feng Shieh

Chien-Li Kuo

Kun-Chi Lin

Fang-Ching Chao

Der-Yuan Wu

Vencent Chang

Uwe Schroeder

Jochen Schacht

Chin-Hui Lee

Chun-Cho Chen

Bo-Jou Lu

Yong-Fa Huang

Huan-Ting Tseng

Nathna Sun

Nai-Lun Chang

Jian-Shin Liou

A system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings.

Transmission mask with differential attenuation to improve ISO-dense proximity

An apparatus, system and method to compensate for the proximity effects in the imaging of patterns in a photolithography process. A light exposure of a photoresist layer is effectuated in predetermined patterns through an exposure mask having light-transmissive openings in correspondence to the predetermined patterns. The exposure mask has areas densely populated with the light-transmissive openings and areas sparsely populated with the light-transmissive openings. Light is attenuated through the densely populated light-transmissive openings by a different amount than through the sparsely populated light-transmissive openings.

To avoid the yield of wafers that undergo immersion lithography influencing by delay of post exposure baking (PEB), an operation system adjusts a speed of inputting the wafers to undergo immersion lithography according to a status of wafers that have finished exposure and are waiting for baking. Therefore, the wafers that have finished exposure are transmitted to be baked efficiently and on time.

Method and related operation system for immersion lithography

The present invention provides a method for designing a mask. First, a main pattern including at least a strip pattern is formed on the mask substrate. A shift feature is added to one end of the strip pattern of the main pattern. Either the phase shift or the optical transmission or both of the shift feature can be adjusted to optimize the resultant critical dimension between line-ends of the main pattern, thus improving pullback of the line-ends of the strip pattern in the main pattern.

Method for designing photomask

There is a grain phenomenon issue of rough sidewall for patterning. Thus, imprecise grain profiles would be observed. As the critical dimensions of integrated circuit microelectronics fabrication device have decreased, the effect of grain phenomenon have become more pronounced. A profile improvement method with a thermal-compressive material and a thermal-compressive process is provided to solve the grain phenomenon issue for baseline of 0.09 um generation and beyond. With this material, the profile can be improved no matter in top view or lateral view. Furthermore, there are 0.1 um IDOF improvement and better physical etching performance.

Profile improvement method for patterning

An invention of lithography process using an improved reflection mask is provided for extreme ultraviolet (EUV) lithography. In the process an incident EUV is transmitted onto the reflection mask at a grazing incident angle. Therefore a reflected EUV develops a pattern image to a photo resist layer on the surface of the wafer, wherein the shape of the pattern image is dependent on the shape of a plurality of reflective regions on the surface of the reflection mask. Specially, the improved reflection mask is more easily fabricated. The surface roughness and the defects of the reflection mask are also more easily controlled. The improved EUV lithography process is more efficient and cheap.

EUV reflection mask and lithographic process using the same

A photomask with desired illumination conditions can be constructed by combining a base pattern of openings with an assist pattern which includes openings that are offset from respectively corresponding openings of the base pattern by a preset angular distance.

Effective assist pattern for nested and isolated contacts

A dual phase shifting mask (PSM)/double exposure lithographic process for manufacturing a shrunk semiconductor device. A semiconductor wafer having a photoresist layer coated thereon is provided. A first phase shift mask is disposed over the semiconductor wafer and implementing a first exposure process to expose the photoresist layer to light transmitted through the first phase shift mask so as to form a latent pattern comprising a peripheral unexposed line pattern in the photoresist layer. The first phase shift mask is then replaced with a second phase shift mask and implementing a second exposure process to expose the photoresist layer to light transmitted through the second phase shift mask so as to remove the peripheral unexposed line pattern.

Phase shifting lithographic process

A phase shifting mask is disclosed in this present invention. The above-mentioned phase shifting mask comprises a quartz layer and a plurality of transmission adjustor layer onto the quartz layer. By employing the above-mentioned phase shifting mask, the material of the transmission adjustors has not to be changed with the light source. Furthermore, the contrast of the phase shifting mask of this invention is better than the contrast of the binary mask and the half-tone mask in the prior art. Therefore, this invention provides a more efficient mask, and the phase shifting mask according to this present invention can improve the resolution in photolithography.

Structure of phase shifting mask

A phase shifting lithographic process capable of creating a shrunk fine line pattern on a photoresist layer coated on a semiconductor wafer is disclosed. A first phase shift mask is prepared, which comprises thereon a first phase shift clear area, a second phase shift clear area situated adjacent to the first phase shift clear area, a vertical control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, and a horizontal opaque area connected to the vertical control chrome line section in an orthogonal manner. A first exposure process is implemented to expose the photoresist layer to light transmitted from clear areas of the first phase shift mask so as to form a vertical fine line image corresponding to the vertical control chrome line section disposed at a boundary between the first phase shift clear area and the second phase shift clear area, a horizontal unexposed area connected to the vertical fine line image in an orthogonal manner, and a peripheral unexposed line pattern. A second phase shift mask is prepared, which comprises thereon a third phase shift clear area, a fourth phase shift clear area situated adjacent to the third phase shift clear area, a horizontal control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area, and a vertical opaque area connected to the horizontal control chrome line section in an orthogonal manner for shielding the vertical fine line image on the photoresist layer. A second exposure process is implemented to expose the photoresist layer to light transmitted from clear areas of the second phase shift mask so as to form a horizontal fine line image corresponding to the horizontal control chrome line section disposed at a boundary between the third phase shift clear area and the fourth phase shift clear area.

A photolithographic process that involves building a sandwich photoresist structure. A first photoresist layer is formed over a substrate. An anti-reflection layer is formed over the first photoresist layer. A second photoresist layer is formed over the anti-reflection layer. A first photo-exposure is conducted and the exposed second photoresist layer is developed to pattern the second photoresist layer and the anti-reflection layer. Using the second photoresist layer and the anti-reflection layer as a mask, a second photo-exposure and a second photoresist development are conducted to pattern the first photoresist layer.

Sandwich photoresist structure in photolithographic process

A method for shrinking critical dimension of semiconductor devices includes forming a first pattern of a photoresist layer on a semiconductor device layer, by performing a blanket exposing process to expose the photoresist layer and the exposed semiconductor device layer to light having a wavelength that can be absorbed by the photoresist layer to provide the photoresist layer with a predetermined energy per unit area, thereby producing photo generated acids therein. A first thermal process is performed to diffuse the photo-generated acids formed within the photoresist layer and to equalize glass transition temperature (T ) of the photoresist layer. A second thermal process is thereafter carried out. The first thermal process is carried out under a temperature lower than T of the photoresist layer.

Method for shrinking critical dimension of semiconductor devices

A method for removing a native oxide layer using hydrogen to react with the native oxide layer is described. Oxygen atoms in silicon dioxide is replaced to achieve the purpose of native oxide removal. Additionally, laser enhancement is used to lower the reaction temperature to between 200&deg;-700&deg; C. The purpose of low-temperature native oxide removal is thus achieved.

Method for removing native oxide

A method of forming the lower electrode of a capacitor capable of withstanding the flushing force produced by a cleaning agent. A lower electrode having a rectangular profile when viewed from the top is provided. The lower electrode is bounded by a pair of ends and a pair of sides. The ends and the sides are linked together. The ends have a wedge shape. The sides have edges that cave in towards the center, thereby forming a recess region between the sides. A flushing operation is carried out using a cleaning solution. The cleaning solution flows from one end of the electrode to the other end along the sides.

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Hsinchu, Taiwan

Benjamin Szu-Min Lin