Utac Headquarters Pte. Ltd.

Agency for Science, Technology and Research

Beng Yeung Ho

Nathapong Suthiwongsunthorn

Rui Huang

Hua Hong Tan

Kriangsak Sae Le

Roel Adeva Robles

Antonio Jr Bambalan Dimaano

Wedanni Linsangan Micla

Nelson Agbisit De Vera

William John Nelson

Poh Leng Wilson Ong

Ranganathan Nagarajan

Ling Xie

Vivek Chidambaram

Bangtao Chen

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Semiconductor packages and methods of packaging semiconductor devices

Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

Methods for singulating semiconductor wafer

The invention relates to a layer arrangement and a wafer level package comprising the layer arrangement, and in particular, the layer arrangement comprises a getter layer and further comprises a sacrificial layer. The wafer level package may be used in microelectromechanical systems (MEMS) packaging at a vacuum level of about 10 mTorr or less such as close to 1 mTorr (i.e. MEMS vacuum packaging).

Layer arrangement and a wafer level package comprising the layer arrangement

Growing community of inventors

Singapore, Singapore

Beng Yeung Ho