International Business Machines Corporation

Benedikt Geukes

Matteo Michel

Manfred Walz

Krishnendu Mondal

Mitesh A Agrawal

Heiko Michel

Derek E Williams

Viresh Paruthi

Wolfgang Roesner

Stephen Gerard Shuma

Bodo Hoppe

Ali S El-Zein

Holger Horbach

Stephen J Barnfield

Klaus-Dieter Schubert

Juergen Wakunda

Martin Doerr

Chung-Lung K Shum

Robert Alan Cargnoni

Michael H Wood

Gavin Balfour Meil

Alvan Wing Ng

Birgit Schubert

Carsten Schmitt

Edward Armayor McQuade

Kilaus-Dieter Schubert

Maya Safieddine

A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.

Logical clock connection in an integrated circuit design

A specification for a modular circuit design includes a mapping from global clock domains to global voltage domains. A processor assigns, to a first instance of a clocked primitive component, a global voltage domain based on which global clock domain clocks the first instance, automatically adds, to the modular circuit design, first power supply rails to power the first instance, and connects the first power supply rails from the first instance to a first power supply for a first global voltage domain. The processor assigns, to a second instance of the clocked primitive component, a second global voltage domain based on which global clock domain clocks the second instance, automatically adds second power supply rails to power the second instance, and connects the second power supply rails to a second power supply for a second global voltage domain. The processor may perform further processing on the updated modular circuit design.

Automating addition of power supply rails, fences, and level translators to a modular circuit design

A processor receives, as input, a first hardware description language (HDL) file defining an entity of a modular circuit design. The first HDL file instantiates, by a storage element declaration in a hardware description language, a storage element within the entity. The first HDL file omits a port map for the storage element. Based on the first HDL file, the processor automatically fully elaborates a port map for the storage element. The processor stores, in data storage, a derived second HDL file defining the entity and including the port map.

Clock mapping in an integrated circuit design

Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.

Automatic detection of clock grid misalignments and automatic realignment

Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Simultaneous scan chain initialization with disparate latches

A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.

On-chip sequence profiler

Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

Protecting chip settings using secured scan chains

Some embodiments include a method for processing a scan chain in an integrated circuit. The method can include: receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; comparing the secret key pattern to a reference key pattern; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

The present invention relates to a method for a self-boot of an electronic device, wherein an external component is accessible through an interface of the electronic device (), the method comprising, determining a boot mode for booting the electronic device, wherein the determined boot mode is defined as a secure boot mode; disabling the interface, thereby prohibiting access to the component through the interface, thereby defining a secure state of the electronic device; loading a first code comprising a sequence of executable instructions to be executed for booting the electronic device; loading a second code, the second code being encrypted; and decrypting the second code and executing the second code, thereby enabling the interface, and switching the electronic device from the secure state to a debugging state.

Method for secure self-booting of an electronic device

A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.

Method for JTAG-driven remote scanning

A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.

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Stuttgart, Germany

Benedikt Geukes