Intel Corporation

Been-Yih Jin

Robert S Chau

Jack T Kavalieros

Suman Datta

Brian S Doyle

Matthew V Metz

Ravi Pillarisetty

Benjamin Chu-Kung

Justin K Brask

Mantu K Hudait

Marko Radosavljevic

Willy Rachmady

Mark L Doczy

Uday Shah

Boyan Boyanov

Nancy M Zelick

Scott A Hareland

Gilbert W Dewey

Anand S Murthy

Stephen M Cea

Reza Arghavani

Shaofeng Yu

Markus Kuhn

Niloy Mukherjee

Amlan Majumdar

Roza Kotlyar

Majumdar Amian

Marko Radosavlievic

Miriam Ruth Reshotko

Douglas W Barlage

Doulgas W Barlage

Suman Datt{dot Over (a)}

Majumdar Amlan

Mantu Hudalt

Anand Murphy

Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Two-dimensional condensation for uniaxially strained semiconductor fins

A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

Extreme high mobility CMOS logic

A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

Germanium-based quantum well devices

Techniques are disclosed for enabling multi-sided condensation of semiconductor fins The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Strain inducing semiconductor regions

A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1&#x2212;xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1&#x2212;yGey and a covering region comprising SiO2 and enclosing the center region.

Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Techniques for forming non-planar germanium quantum well devices

Embodiments of an apparatus and methods of providing a quantum well device for improved parallel conduction are generally described herein. Other embodiments may be described and claimed.

Apparatus and methods for improving parallel conduction in a quantum well device

The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Isolation for nanowire devices

Strain-inducing semiconductor regions

Growing community of inventors

Lake Oswego, OR, United States of America

Been-Yih Jin