Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique

Weebit Nano Ltd.

Stmicroelectronics (rousset) Sas

Bastien Giraud

Jean-Philippe Noel

Olivier Thomas

Sylvain Clerc

Adam Makosiej

Fady Abouzeid

Yvain Thonnart

Philippe Flatresse

Michel Harrand

Elisa Vianello

Valentin Gherman

Matthieu Le Boulaire

Maud Vinet

Philippe Roche

Francois Andrieu

Remy Berthelon

François Andrieu

Jean-Michel Portal

Amara Amara

Samuel Evain

Ilan Sever

Alexandre Levisse

Kaya Can Akyel

Santhosh Onkaraiah

Lorenzo Ciampolini

Cyrille Laffond

Avishek Biswas

Bertrand Pelloux-Prayer

Thomas-Medhi Benoist

Reda Boumchedda

Haithem Ayari

Yves Maneglia

Emilien Bourde-Cice

Sebastien Ricavy

Yasser Moursy

Sébastien Ricavy

Réda Boumchedda

A static random access memory device includes a memory matrix provided with at least one set of SRAM memory cells and a circuit for initializing cells of the set, the setting circuit being able to carry out various setting types and in particular a 'deterministic' setting in which the cells are established at an imposed value and to carry out a “free” setting in which the cells are established at a value that depends on their manufacturing method.

SRAM with reconfigurable setting

A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

Write method for differential resistive memories

An electroforming process for a resistive memory of a memory device including a memory controller, an encoder computing an inversion-invariant linear error correction code, and a write device connected directly to the encoder. An electroforming device performing electroforming through write operations to such a resistive memory and to a method for checking a write operation.

Electroforming process using an inversion-invariant linear ECC, and associated device

A Memory device comprising a matrix of memory cells, the matrix being provided with at least one first column, the device also being provided with a test circuit configured to perform a test phase during a read operation to indicate whether or not the proportion of cells in said column storing the same logical data, particularly a logical '1', is greater than a predetermined threshold.

Circuit for detection of predominant data in a memory cell

A memory circuit including a plurality of elementary cells arranged in a plurality of arrays, each including a plurality of rows and a plurality of columns, and wherein: the elementary cells having the same coordinates in the different arrays share a same first conductive track; and in each array, the elementary cells of a same row of the array share a same second conductive track and a same third conductive track.

Memory circuit

A memory circuit including a plurality of elementary cells arranged in an array of rows and of columns, and a control circuit capable of implementing an operation of vertical reading of a word from a column of the array.

Memory circuit capable of implementing calculation operations

A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M&#x2212;1, are coupled together.

Partitioned memory circuit capable of implementing calculation operations

The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

3D SRAM circuit with double gate transistors with improved layout

The invention relates to a resistive memory () including resistive elements, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device () for switching the resistance of at least one resistive element selected from among the resistive elements between the high and low values, the device including a first circuit capable of applying an increasing voltage across the selected resistive element while the selected resistive element is at the high value or at the low value, a second circuit capable of detecting the switching of the resistance of the selected resistive element, and a third circuit capable of interrupting the current flowing through the selected resistive element on detection of the switching.

Device and method for writing data to a resistive memory

A memory circuit including cells connected in rows and in columns, each cell including a programmable resistive element and a control transistor, the memory circuit further including a control circuit capable of, during a cell programming phase: applying a first voltage to a control conductive track of the column including the cell; applying a second voltage to the first control conductive track of the row including the cell; applying a third voltage capable of turning on the cell control transistor to a second row control conductive track including the cell; and applying a fourth voltage capable of turning off the control transistors to the control conductive tracks of columns which do not include the cell.

Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof

An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground planes, a buried oxide layer and first and second wells, under the ground planes. The first well and the first ground plane have the same doping and the second well and the second ground plane have the same doping. The first and second cells are adjoined and their transistors are aligned in a first direction. The wells of the first cell and the first well of the second cell are doped opposite of the second well. A control device applies a first electrical bias to the wells with the first doping and a second electrical bias to the well with the second doping. The transistors of the first cell and second cell have different threshold voltage levels.

Integrated circuit comprising transistors with different threshold voltages

A memory device includes a matrix of several columns of SRAM memory cells each including transistors forming a memory point, a read port and a write port, and such that the transistors of the read port and/or the P-type transistors include a second well with a conductivity type opposite that of a first well of the other transistors. The memory device also includes a polarization unit for the second wells, able to select and apply polarization potentials on the second wells, including a memory circuit of the polarization states of the second wells for each column or group of columns and a selection circuit applying a polarization potential on the second wells according to one of the values received as input, as a function of the stored polarization state associated with the column or group of columns.

Device with SRAM memory cells including means for polarizing wells of memory cell transistors

A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.

Programmable-resistance non-volatile memory

A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the logic cells. A back gate potential difference ('BGPD') of a pMOS-FET is a difference between its source potential less its back-gate potential, and vice versa for an nMOS-FET. The method includes applying first and second back gate potential difference (BGPD) to a logic cell's first and second FETs and either applying a third BGPD to a third FET, wherein the third BGPD is positive and greater than the first BGPD applied, which is applied concurrently, or applying a fourth BGEPD to a fourth FET, wherein the fourth BGPD is positive and greater than the second BGPD that is applied concurrently.

Method for controlling an integrated circuit

The invention relates to a resistive memory including resistive elements, the resistance of each resistive element being capable of alternating between a high value and a low value, the memory further including a device for switching the resistance of at least one selected resistive element between the high and low values. The device includes a first circuit capable of circulating a first current through a first reference resistive component (R), a second circuit capable of circulating a second current proportional to the first current through the selected resistive element, a third circuit capable of detecting the switching of the resistance of the selected resistive element from the comparison of the voltage across the first reference resistive component with the voltage across the selected resistive element, and a fourth circuit capable of interrupting the second current on detection of the switching.

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Voreppe, France

Bastien Giraud