International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Bartlet H Deprospo

Lawrence Alfred Clevenger

Michael Rizzolo

Benjamin David Briggs

Christopher J Penny

Huai Huang

Nicole A Saulnier

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device

Embodiments are directed to a support apparatus. The support apparatus might comprise a body configured to support an entity. The body might comprise a material that has a physical property. The support apparatus might further comprise a coupler system configured to couple electric current from a power source to the material. The material is arranged such that coupling an electric current to the material changes the physical property of the material. Embodiments are further directed to a method. The method might comprise forming one or more cavities in a support apparatus. The method might further comprise providing one or more couplers in electrical contact with each of the one or more channels. The method further comprises filling each of the one or more cavities with a fluid that has electrically changeable rigidity. Finally, the method might comprise connecting a power source to each of the one or more couplers.

Dynamic rigidity mechanism

A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.

Self-aligned airgaps with conductive lines and vias

A method (and structure) includes performing an initial partial anneal of a metal interconnect overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer. Orientation of an early recrystallizing grain at a specific location on a top surface of the metal overburden layer is determined, as implemented and controlled by a processor on a computer. A determination is made whether the orientation of the early recrystallizing grain is desirable or undesirable.

Location-specific laser annealing to improve interconnect microstructure

A document including a Directed Self-Assembly (DSA) pattern including a unique and randomized pattern embedded on the document, where the DSA is formed by using two different-length polymer chains.

Structure of implementing a directed self-assembled security pattern

A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

Enhanced self-alignment of vias for a semiconductor device

A method of forming a semiconductor device includes forming a porous dielectric layer including a recessed portion, forming a conductive layer in the recessed portion of the porous dielectric layer, and forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer.

An anti-counterfeiting method, system, and non-transitory computer readable medium including a transfer circuit configured to transfer a Directed Self-Assembly (DSA) pattern including a unique and randomized pattern onto a strip, an embedding circuit configured to embed the strip on a document, and a verification circuit configured to verify that the unique and randomized pattern embedded on the document corresponds to the document.

Structure, system, method, and recording medium of implementing a directed self-assembled security pattern

Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.

Growing community of inventors

Goshen, NY, United States of America

Bartlet H Deprospo