Siliconix Incorporated

Nxp B.v.

Cyntec Company

Barry Lin

Shih Chang Liao

Duen Jen Cheng

Techniques are disclosed herein for forming a dual flat no-leads semiconductor package. The techniques begin with a package assembly that includes multiple non-singulated packages. The semiconductor package assembly includes a lead frame assembly having dies coupled thereto. A mold encapsulation covers at least portions of the dies and exposes a plurality of leads. A first cutting step exposes sidewalls of leads of the lead frame. An electroplating step deposits a plating on the exposed leads. A second cutting step cuts through the mold encapsulation aligned with the step cut sidewalls. A third cutting step perpendicular to the step cuts and is made through the lead frame and mold encapsulation to singulate the dies into individual packages.

Semiconductor package having side wall plating

Methods are disclosed herein for forming wettable flanks on quad flat no-leads semiconductor packages. The methods may begin with a package assembly having multiple non-singulated packages. The package assembly includes a lead frame assembly having dies coupled thereto. A mold encapsulation covers the dies and exposes portions of leads. An electroplating step deposits plating on the exposed portions of the leads. First and second series of parallel step cuts are made between the die packages to form sidewalls of wettable flanks. The first and second series of parallel step cuts are perpendicular to each other. These cuts are made at a depth to cut fully through the lead frame but not fully through the mold encapsulation. After the first and second series of parallel step cuts, the wettable flanks are plated using an electroless method. A third and fourth series of cuts singulates the assembly into discrete QNF semiconductor packages.

An integrated circuit leadframe device supports various chip arrangements. As consistent with various embodiments, a leadframe includes a plurality of banks of conductive integrated circuit chip connectors. Each bank has a plurality of conductive strips respectively having an end portion, the end portions of each of the strips in the bank being substantially parallel to one another and arranged at an oblique angle to end portions of strips in at least one of the other banks. Each of the end portions has a tip extending to an interior portion of the leadframe device and separated from the other tips by a gap. A fastening material is arranged on at least some of the conductive strips and configured to fasten an integrated circuit chip to the conductive strips

Leadframe circuit and method therefor

The present invention discloses a resistive circuit. The resistive circuit includes a plurality of resistor networks disposed on a substrate. The resistor networks also includes a plurality of resistive circuit elements. The resistor networks further includes a plurality of termination contacts each connected to one of the resistive circuit elements. Each of the termination contacts is disposed on an edge of the substrate and each of the termination contacts is separated from a next termination contact by an edge trench disposed on the edge of the substrate whereby a distance across the edge trench defining a pitch between the termination contacts.

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Kaohsiung, Taiwan

Barry Lin