Raytheon Company

Barry J Liles

H Barteld Van Rees

Colin Steven Whelan

Mark S Durschlag

James G Oakes

A method and structure for reducing cracks in a dielectric in contact with a metal structure. The metal structure comprises a first metal layer; a second metal layer disposed on, and in contact with the first metal layer, the second metal layer being stiffer than the first metal layer; a third metal layer disposed on, and in contact with the second metal layer, the second metal layer being stiffer than the third metal layer. An additional metal is included wherein the dielectric layer is disposed between the metal structure and the additional metal.

Method and structure for reducing cracks in a dielectric layer in contact with metal

A semiconductor structure is described having a first electrode and a second electrode disposed on a surface of the structure and a bridging conductor connected between the first electrode and the second electrode. The bridging conductor includes a plurality of layers of different metals wherein the plurality of layers of different metals includes a layer of refractory metal adjacent a layer of electrically conductive metal. In a preferred embodiment, the refractory metal is titanium and the electrically conductive metal is gold. With such an arrangement, a semiconductor structure is provided which is effective in preventing restructuring due to mechanical stresses induced in the metal by dissimilar thermal expansion coefficients when electrical pulsing cycles the temperature of the semiconductor structure.

Semiconductor structures and method of manufacturing

A field effect transistor includes a substrate of gallium arsenide having a resistivity of at least about 10.sup.7 ohm/cm and a first buffer layer of gallium arsenide disposed over the substrate having a deep level acceptor dopant incorporated into the buffer layer to compensate for donor dopants incorporated into the buffer layer. The concentration of the donor dopants and the acceptor dopant are controlled to provide the buffer layer with a predetermined resistivity characteristic of about 10.sup.7 -10.sup.8 ohm/cm. The concentration of the deep acceptor dopant is substantially constant at about 10.sup.16 acceptors/cc throughout the first buffer layer. The buffer layer preferably has a thickness of at least 2 microns and preferably between 5 and 30 microns. A second buffer layer is disposed over the first buffer layer having a monotonically declining concentration of chromium dopant from about 10.sup.16 to less than about 10.sup.14 acceptors/cc. An active layer and contact layer of suitably n-type doped gallium arsenide are consecutively disposed over at least portions of the second buffer layer.

Semiconductor devices having compensated buffer layers

A field effect transistor includes a semi-insulating substrate having a doped compensated buffer layer. Such compensated buffer layer is doped with a species which provides deep level acceptors to compensate for background donor doping of the buffer layer and to thus provide the semi-insulating buffer layer. The compensated buffer layer is used to isolate subsequent layers from crystal defects in the substrate. A thin shielding layer having a dopant concentration of 10.sup.14 -3.times.10.sup.15 atoms/cm.sup.3 and a dopant conductivity opposite to that of the dopant used to compensate the buffer layer is disposed over the buffer layer. An active layer is then disposed over the shielding layer and areas in the active layer are provided for source, drain, and gate electrodes. By providing the doped shielding layer, a small amount of conduction is provided in the shielding layer which prevents the build-up of charge in the buffer layer caused by ionization of the deep-level acceptor. The shielding layer also prevents the out-diffusion of the dopant species of the buffer layer into the active layer of the device.

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Westborough, MA, United States of America

Barry J Liles