Waferscale Integration, Inc.

Barmak S Sani

Boaz Eitan

Alexander Shubat

A structure and method are provided for accurately compensating for the neighbor effect in reading the state of a memory cell in a virtual ground memory array. When the supply voltage Vcc of the memory array increases above a selected maximum value Vccmax, a programmed memory cell reads as an unprogrammed cell. Due to the neighbor effect, a neighboring cell, which was initially unprogrammed during the programming of the memory cell but was subsequently also programmed, causes Vccmax of the memory cell to be lower in a read cycle than in the previous program/verify cycle, resulting in discarding the memory device. In accordance with the present invention, circuitry activated during the read cycle compensates for the neighbor effect by including an unprogrammed replica EPROM transistor identical to the memory cell in parallel with the neighbor of the memory cell being read. This unprogrammed replica EPROM transistor essentially replaces the effect of the actual neighbor memory cell on the memory cell being read and thus ensures that the Vccmax of the memory cell in the read cycle is equal to or greater than the corresponding Vccmax of the memory cell in the program/verify mode.

Structure and method for compensating for programming threshold shift

A novel circuit is coupled to a memory device sense amplifier and a memory device output pin for driving the output pin with data. The circuit includes a first inverter (18) and a second inverter (100) coupled to the first inverter. Transfer gates (30, 104) are coupled across the input and output leads of the first and second inverters, respectively. During a first mode of operation, the first and second transfer gates are closed and the second inverter is three-stated so that the input and output leads of the first and second inverters are held at a voltage between VCC and ground. When it is desired to drive the memory device output pin with data, the first and second transfer gates open, and the second inverter leaves the three-state mode and goes into a low output impedance mode. Because the input and output leads of the first and second inverters are held at a voltage between VCC and ground when the transfer gates are closed, when the transfer gates open, the delay between the time the transfer gates open and the time valid output data appears on the output lead of the second inverter is minimized. The second inverter comprises large transistors and can therefore provide a large output current. However, because the second inverter is three-stated when the second transfer gate is closed, the circuit draws minimal power when the first and second transfer gates are closed.

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Palo Alto, CA, United States of America

Barmak S Sani