Infineon Technologies Ag

Formfactor, Inc.

Barbara Vasquez

Harry Hedler

Thorsten Meyer

Roland Irsigler

Gerd Frankowsky

Benjamin N Eldridge

Gaetan L Mathieu

A Nicholas Sporck

Makarand S Shinde

Igor Y Khandros

Charles A Miller

Georg Meyer-Berg

Axel Brintzinger

Jochen M&uuml;ller

Bruce Barbara

Sylvia Baumann Winter

David Wallis

Stefan Ruckmich

Semiconductor dies are stacked offset from one another so that terminals located along two edges of each die are exposed. The two edges of the dies having terminals may be oriented in the same direction. Electrical connections may connect terminals on one die with terminals on another die, and the stack may be disposed on a wiring substrate to which the terminals of the dies may be electrically connected.

Stacked die module

A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, or pluggable and unpluggable enabling movement over a range of positions.

Mechanically reconfigurable vertical tester interface for IC probing

A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.

Method for producing an electronic component, especially a memory chip

A wafer test assembly includes multiple probe head substrates arranged like tiles with connectors attached to one side and probes supported on the opposing side. In one embodiment, flexible cable connectors directly connect the connectors on the probe head tile to a test head, while in another embodiment the flexible cables connect the probe head tile to a PCB providing horizontal routing to test head connectors. In one embodiment, leveling pins provide a simplified support structure connecting to a retaining element attached to the tiles to provide for applying a push-pull leveling force. A test head connector interface frame enables rearrangement of connectors between the test head and the probe card to provide for both full wafer contact or partial wafer contact. The test head connectors are rearranged by being slidable on rails, and unpluggable using pins, enabling movement over a range of positions.

A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps:

Process for producing a component module

An electronic component has a semiconductor chip and microscopically small flip-chip contacts belonging to a rewiring plate, on which macroscopically large elastic external contacts are arranged. The rewiring plate has a wiring support made of polycrystalline silicon, amorphous glass, or metal. Furthermore, the present invention relates to a method for the production of a suitable wiring support and of the electronic component.

Electronic component having at least one semiconductor chip and flip-chip contacts, and method for producing the same

A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection regions

The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.

Semiconductor circuit module and method for fabricating semiconductor circuit modules

A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.

Method of producing a semiconductor component having a compliant buffer layer

A process for producing a semiconductor chip having contact elements protruding on one chip side within the context of wafer level packaging, the chip side provided with the contact elements being coated with a covering compound forming a protective layer, from which the protruding contact element project.

Process for producing a semiconductor chip

The present invention provides a method of connecting an integrated circuit to a substrate and a corresponding circuit arrangement. Connecting occurs by performing the steps of: providing a main area (HF) of the integrated circuit (), which has an electrical contacting region (), with a mechanical supporting structure (); providing a solderable surface region () of the mechanical supporting structure (); providing a solderable terminal region (), which is electrically connected to the electrical contacting region (), on the main area (HF) of the integrated circuit (); providing a main area (HF) of the substrate () with a first soldering region (), which can be aligned with the solderable surface regions (), and with a second soldering region (), which can be aligned with the solderable terminal region (); and simultaneous soldering of the surface regions () to the first soldering region () and of the terminal region () to the second soldering region ().

Connection of integrated circuit to a substrate

The present invention provides a method for producing a semiconductor device, with the steps of: applying an interconnect level () to a semiconductor substrate (); structuring the interconnect level (); and applying a solder layer () on the structured interconnect level () in such a way that the solder layer () assumes the structure of the interconnect level (). The present invention likewise provides such a semiconductor device.

Method for producing a semiconductor device and corresponding semiconductor device

A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant interconnect element defines a chamber between the first surface of the substrate and a surface of the compliant interconnect element. The compliant interconnect element can be a compliant layer. The compliant layer can be formed of a polymer, such as silicone. A conductive layer can be disposed on the compliant layer, in contact with a contact pad on the semiconductor substrate. A method for forming a semiconductor structure includes providing a semiconductor substrate and providing a compliant interconnect element on a first surface of the substrate, so that the compliant interconnect element defines a chamber between the compliant interconnect element and the first surface of the substrate.

Compliant relief wafer level packaging

A contact connection between a semiconductor chip and a substrate has a conductive adhesive extending between each contact of the chip and the substrate. The conductive adhesive includes a matrix component, a filler component, a hardener component and at least one decomposable component so that after curing at a curing temperature T, the adhesive can be decomposed either by applying thermal energy at a temperature T&#x3e;Tor by radiation so that the two contact surfaces can be separated smoothly. After separation the purposes of replacing a defective semiconductor chip, a second chip can be mechanically connected by applying the adhesive and curing it.

Method producing a contact connection between a semiconductor chip and a substrate and the contact connection

The invention creates a method for connection of circuit units () which are arranged on a wafer (), in which the wafer () is fitted to a first film (), the wafer () is sawn such that the circuit units () which are arranged on the wafer () are separated, the functional circuit units () are picked up by means of a handling device () and are placed down on a second film () by means of the handling device (), so as to produce a separation distance which can be predetermined between connection contacts of the circuit units ().

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Orinda, CA, United States of America

Barbara Vasquez