Samsung Electronics Co., Ltd.

University-Industry Cooperation Group of Kyung Hee University

Bangweon Lee

Se-Ho You

Jaechoon Kim

Seunggeol Ryu

Seongho Shin

Seokkan Ki

Youngsuk Nam

Seungtae Hwang

Seokhyun Lee

Kyoung Lim Suk

Kyung Suk Oh

Jae Choon Kim

Eungchang Lee

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a first molding layer on the package substrate and surrounding the first semiconductor chip, a redistribution layer on the first molding layer, a first through via that vertically penetrates the first molding layer and connects the package substrate to the redistribution layer, a second semiconductor chip mounted on the redistribution layer, a second molding layer on the redistribution layer and surrounding the second semiconductor chip, and a second through via that vertically penetrates the second molding layer and is connected to the redistribution layer. A first width of the first through via is less than a second width of the second through via. The second through via is electrically floated from a signal circuit of the second semiconductor chip.

Semiconductor package

A semiconductor package including a substrate and at least one semiconductor chip on the substrate may be provided. The substrate may include a body layer having a top surface and a bottom surface, a first thermal conductive plate on the top surface of the body layer, the first thermal conductive plate connected to a ground terminal of the semiconductor chip, and a thermal conductive via penetrating the body layer and being in contact with the first thermal conductive plate.

A method of manufacturing a thermal interface material may include mixing fine particles with an acidic solution to remove a first oxide layer from a surface of each of the fine particles, injecting a liquid metal into the acidic solution to remove a second oxide layer from a surface of the liquid metal and for the fine particles from which the first oxide layer is removed in the acidic solution to penetrate into the liquid metal from which the second oxide layer is remove, and extracting the liquid metal including the fine particles therein from the acidic solution.

Thermal interface material, method of manufacturing the same, and semiconductor packages including the same

A semiconductor package may include a package substrate, a semiconductor chip on the package substrate, a heat dissipation member on the semiconductor chip, and a first thermal interface material coated on an upper surface of the semiconductor chip to bond the semiconductor chip and the heat dissipation member. The first thermal interface material may include a liquid metal and fine particles disposed inside the liquid metal. The fine particles may have no oxide layer on a surface thereof. A volume percentage of the fine particles in the liquid metal including the fine particles therein may be about 1% to about 5%. A thermal conductivity of the liquid metal including the fine particles therein may be equal to or more than about 40 W/m·K.

Thermal interface material and semiconductor packages including the same

A semiconductor device may include a substrate, a first semiconductor chip buried in the substrate, a first antenna pattern, a second antenna pattern, and outer terminals. A bottom surface of the substrate may include first and second regions spaced apart from each other. The first semiconductor chip may have a first active surface that is directed to the top surface of a core portion of the substrate. The first antenna pattern may be provided on the top surface of the substrate and electrically connected to the first semiconductor chip. The outer terminals may be provided on the first region of the bottom surface of the substrate, and the second antenna pattern may be provided on the second region of the bottom surface of the substrate.

Growing community of inventors

Yongin-si, South Korea

Bangweon Lee