Exar Corporation

Rite Taste, LLC

Sierra Semiconductor

Graphene-dx, Inc.

Other

Bahram Fotouhi

Roubik Gregorian

Edward Alvin Greenfield

Mohammad Esmaail Taslim

Reza Mollaaghababa

Mehdi Abedi

Kashayar Javaherian

Mohammed Fotouhi

Namal Nawana

Bahman Farzan

Mir Bahram Ghaderi

Pekka Ojala

Saied Rafati

Robert Alan Brannen

Loi Thanh Le

Kashayar Java-Herian

Mohammad Fotouhi

A processing and detection system for detecting presence of at least one gluten protein in a food sample comprises a food processor including: a reservoir containing a process liquid for processing the food sample; a body that comprises a chamber configured to receive the food sample; and a pressing surface configured to press on the reservoir to cause the process liquid to exit the reservoir and mix with the food sample, thereby generating a processed food liquid; and an exit port configured to conduct the processed food liquid out of the food processor; and a cartridge including: at least one sensor configured to receive the processed food liquid and to generate an electrical signal in response to interaction with the at least one gluten protein in the processed food liquid, and an analyzer in electrical communication with the at least one sensor for detecting the electrical signal and determining the presence of the at least one gluten protein in the food sample based on the detected electrical signal.

Device and method for chemical analysis

Methods and devices for detecting a target agent of interest, e.g., a pathogen, in a sample are described herein. In some embodiments, a sensor is provided that can include a substrate, a graphene layer disposed on a surface of said substrate, and a protein bound to said graphene layer. The protein can be capable of binding to one or more target agents of interest, e.g., pathogens, etc. The binding of the protein to the one or more target agents of interest can generate a change in an electrical property of the graphene layer.

To maintain the amplitude of an oscillating signal within a defined range, the detected peak level of the oscillating signal is compared to a reference voltage. If the detected peak level is determined as being greater than the reference voltage, the common source/drain voltage of a differential amplifier driving the crystal oscillator across its input terminals is reduced so as to lower the amplitude of the oscillation signal. If the detected peak level is determined as being smaller than the reference voltage, the common source/drain voltage of the differential amplifier driving the crystal oscillator is increase so as to raise the amplitude of the oscillation signal.

Amplitude regulated crystal oscillator

A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are complementary with respect to a voltage present at the center of the resistor segment disposed in that decoder. A second decoding stage receives the first and second voltages delivered by each of the N decoders and delivers two of these voltages, that are complementary with respect to a voltage present at the center of the resistor, to a pair of third and fourth output nodes.

High speed differential resistive voltage digital-to-analog converter

A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to the voltage output of the operational amplifier. The insertion of this semiconductor element provides the ability to programmably connect the parasitic capacitance to somewhere other than ground. By connecting the parasitic capacitance to the voltage input or voltage output, the ground connection is eliminated, eliminating the pole introduced by the parasitic capacitance.

Frequency compensation of wide-band resistive gain amplifier

A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the first and second transistors off during power off conditions.

CMOS transmission gate with high impedance at power off

The present invention provides a short circuit power limiter circuit having a current sensor and a power limiter. The short circuit sensor sends a short circuit flag signal to the power limiter when the short circuit sensor detects a short circuit condition in a target circuit. The power limiter then reduces the power consumption of the target circuit. In a specific example, the power limiter toggles a particular portion of the target circuit on and off to reduce the circuit's average short circuit power consumption. This cycle is repeated as long as a short circuit condition exists.

Short circuit power limiter

A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on during normal operation. A protection circuit will turn off the NMOS and PMOS transmission gate transistors when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gates of the biasing transistors and the pad to turn the biasing transistors off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.

I/O pad overvoltage protection circuitry

An input termination circuit with high impedance at power off, which includes a first transistor coupled between a first terminal and a second terminal. The input termination circuit also includes a control circuit that monitors voltages on the first and second terminals and a first voltage source. During power off conditions, the control circuit couples the gate of the first transistor to a voltage that will keep the first transistor off. The first transistor remains off even when the voltage levels at the first and second terminals vary wildly.

Input termination with high impedance at power off

An indirect current sensing circuit and method for replicating an output current is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power as well as optimizing output impedance. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect current sensing circuit and its method of current limiting and output impedance optimization, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Wide-band replica output current sensing circuit

A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby preventing forward biasing of the P&plus;/n-well diode.

Power down circuit for high output impedance state of I/O driver

The present invention provides a compensation circuit having a first and a second compensation transistor. The compensation circuit is configured for tying a transconductance, gm, of a first and a second output transistor to a conductance, gds, of the the first and second compensation transistors, respectively, such that a gm-to-gds ratio becomes fixed. The tying stabilizes and prevents movement of the location of the compensation zero. The compensation zero is created by the compensation circuits. The present invention also provides a translinear loop provided by an output and a biasing circuit. The translinear loop includes a first and a second biasing transistor and a first and a second output transistor. The first and second biasing transistors are configured to control the current flow through the first and second output transistors. The biasing circuit also includes a feedback circuit configured for matching the biasing parameters, vgs and vds, of the first and second biasing transistors to those of the first and second output transistors.

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Cupertino, CA, United States of America

Bahram Fotouhi