Hynix Semiconductor Inc.

Skhynix Inc.

Baek Mann Kim

Dong Ha Jung

Jeong Tae Kim

Seung Jin Yeom

Young Jin Lee

Soo Hyun Kim

Nam Yeal Lee

Joon Seok Oh

Sun Woo Hwang

Jae Hong Kim

Jun Ki Kim

Chang Soo Park

Yong Seok Eun

Kwan Yong Lim

Kyong Bong Rouh

Noh Jung Kwak

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuOlayer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuOlayer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.

Semiconductor memory device having vertical transistor and buried bit line and method for fabricating the same

A metal line in a semiconductor device includes an insulation layer formed on a semiconductor substrate. A metal line forming region is formed in the insulation layer. A metal line is formed to fill the metal line forming region of the insulation layer. And a diffusion barrier that includes an amorphous TaBN layer is formed between the metal line and the insulation layer. The amorphous TaBN layer prevents a copper component from diffusing into the semiconductor substrate, thereby improving upon the characteristics and the reliability of a device.

Metal line of semiconductor device having a diffusion barrier with an amorphous TaBN layer and method for forming the same

An electrical conductor having a multilayer diffusion barrier of use in a resultant semiconductor device is presented. The electrical conductor line includes an insulation layer, a diffusion barrier, and a metal line. The insulation layer is formed on a semiconductor substrate and having a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a multi-layered structure made of TaN layer, an MoOlayer and an Mo layer. The metal line is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Electrical conductor line having a multilayer diffusion barrier for use in a semiconductor device and method for forming the same

A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNlayer, a W&#x2014;N&#x2014;B ternary layer, and a Ti&#x2014;N&#x2014;B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.

Metal line of semiconductor device without production of high resistance compound due to metal diffusion and method for forming the same

A metal line having a MoSi/Mo diffusion barrier of a semiconductor device and corresponding methods of fabricating the same are presented. The metal line includes an insulation layer, a diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and has a stack structure composed of a MoSilayer and a Mo layer. The metal layer is formed on the diffusion barrier which fills in the metal line forming region of the insulation layer.

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A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer has a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier includes a multi-layered structure that includes an MoBlayer, an MoBNlayer and an Mo layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Metal line of semiconductor device having a multilayer molybdenum diffusion barrier and method for forming the same

An insulation layer is formed on a semiconductor substrate so as to define a metal line forming region. A diffusion barrier having a multi-layered structure of an MoSilayer, an MoSiNlayer, and an MoNlayer is formed on a surface of the metal line forming region. A metal layer is formed on the diffusion barrier so as to fill the metal line forming region of the insulation layer.

Metal line of semiconductor device having a diffusion barrier and method for forming the same

A multi-layer metal wiring of a semiconductor device and a method for forming the same are disclosed. The multi-layer metal wiring of the semiconductor device includes a lower Cu wiring, and an upper Al wiring formed to be contacted with the lower Cu wiring, and a diffusion barrier layer interposed between the lower Cu wiring and the upper Al wiring. The diffusion barrier layer is formed of a W-based layer.

Multi-layer metal wiring of semiconductor device preventing mutual metal diffusion between metal wirings and method for forming the same

A multi-layered metal line of a semiconductor device and a process of forming the same are described. The multi-layered metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is subsequently formed on the semiconductor substrate including the lower metal line and has an upper metal line forming region that exposes a portion of the lower metal line. A diffusion barrier formed on a surface of the upper metal line forming region of the insulation layer. The diffusion barrier includes a W&#x2014;B&#x2014;N ternary layer. An upper metal line is finally formed on the diffusion barrier to fill the upper metal line forming region of the insulation layer.

Multi-layered metal line having an improved diffusion barrier of a semiconductor device and method for forming the same

A metal line having a multi-layered diffusion layer in a resultant semiconductor device is presented along with corresponding methods of forming the same. The metal line includes an insulation layer, a multi-layered diffusion barrier, and a metal layer. The insulation layer is formed on a semiconductor substrate and has a metal line forming region. The multi-layered diffusion barrier is formed on a surface of the metal line forming region defined in the insulation layer. The diffusion barrier includes a VBlayer, a CrV layer and a Cr layer. The metal layer is formed on the diffusion barrier which substantially fills in the metal line forming region of the insulation layer to eventually form the metal line.

Metal line having a multi-layered diffusion layer in a semiconductor device and method for forming the same

A metal line of a semiconductor device having a diffusion barrier including CrBand a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrBlayer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrBlayer.

Metal line of semiconductor device having a diffusion barrier including CRxBy and method for forming the same

A multi-layered metal line of a semiconductor device includes a semiconductor substrate; a lower metal line formed on the semiconductor substrate and recessed on a surface thereof; an insulation layer formed on the semiconductor substrate including the lower metal line and having a damascene pattern for exposing a recessed portion of the lower metal line and for delimiting an upper metal line forming region; a glue layer formed on a surface of the recessed portion of the lower metal line; a first diffusion barrier formed on the glue layer to fill the recessed portion of the lower metal line; a second diffusion barrier formed on the glue layer and the first diffusion barrier; a third diffusion barrier formed on the second diffusion barrier and a surface of the damascene pattern; and an upper metal line formed on the third diffusion barrier to fill the damascene pattern.

Growing community of inventors

Gyeonggi-do, South Korea

Baek Mann Kim