Globalfoundries Inc.

Blobalfoundries Inc.

Ayman Hamouda

Norman Chen

Ian P Stobert

Chidam Kallingal

Mohamed Elsayed Mohamed Lotfy Gheith

Mohab Anis

The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Curvilinear mask models

Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.

Model-based generation of dummy features

A method of providing self-aligned via (SAV) awareness in optical proximity correction (OPC) includes identifying non-SAV edges, identifying any lower metal structure that is within a critical distance from the non-SAV edges, and defining replacement non-SAV edges proximate to the lower metal structure using a distance constraint that is evaluated as part of the OPC objective function to redefine the mask solution and relocate at least one non-SAV edge away from the lower metal structure.

Methodology for model-based self-aligned via awareness in optical proximity correction

A method for modifying an integrated circuit layout design includes providing an initial multiple-patterned circuit layout design comprising a first pattern exposure and a second pattern exposure; modifying the initial multiple-patterned circuit layout design by providing a subresolution assist feature to the first pattern exposure; determining whether the presence of any overlapping areas between the subresolution assist feature of the first pattern exposure and the second pattern exposure; and further modifying the initial multiple-patterned circuit layout design by: maintaining the size of any portion of the subresolution assist feature in the overlapping areas; and shrinking the size of any portion of the subresolution assist feature that is not in the overlapping areas.

Methods for modifying an integrated circuit layout design

Embodiments of the present invention provide a system and method for SAV (self-aligned via) retargeting. The SAV (Self Aligned Vias) process aids in the alignment of the vias with the metal above (Mx+1) during the dual damascene process. The retargeting enables an increase the area of the via during photolithography without affecting the final critical dimension. SAV retargeting is the via retargeting during the mask tape-out to reshape the via and protect it against possible via-to-Mx+1 overlay error. With embodiments of the present invention, the via edge movement is linked to the actual driver behind the SAV retargeting, which is maintaining a minimum area coverage with the metal above at extreme overlay error conditions. Accordingly, for a via edge to get SAV retargeted, a calculation is first made to determine how much its opposite via edge is subject to be cut during SAV due to overlay error.

Method and system for via retargeting

Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts

Methods for retargeting a via and for fabricating a semiconductor device with a retargeted via are provided. In one embodiment, a method for retargeting a via includes drawing a lower metal layer shape, drawing a via shape for overlying the lower metal layer shape, and drawing an upper metal layer shape for overlying the via shape to create an interconnection area between the via shape and the upper metal layer shape. The method includes determining a potential area loss of the interconnection area during integrated circuit fabrication processing. The method further includes enlarging the via shape to compensate for the potential area loss.

Methods for retargeting vias and for fabricating semiconductor devices with retargeted vias

Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer. The method further includes altering the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, and the second via further being in proximity to the first via. Further, the method includes further altering the initial circuit layout design by providing a subresolution assist feature in proximity to the second via.

Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation. Still further, the method includes modifying the fragmented layout design by moving the at least one fragment in accordance with the required movement to generate a modified layout design and performing optical proximity correction on the modified layout design.

A method of SRAF printing using etch-aware SRAF print avoidance engines and the resulting device are provided. Embodiments include performing mask to resist simulations for a mask having both a plurality of features to be formed on a substrate and a plurality of sub resolution assist features (SRAFs); detecting SRAFs of the plurality that will print through to a resist; checking dimensions of the detected SRAFs to determine whether one or more of the SRAFs will etch through to the substrate; modifying the one or more of the SRAFs; and forming the mask after the one or more of the SRAFs have been modified.

Growing community of inventors

Fishkill, NY, United States of America

Ayman Hamouda