Ikanos Communications, Inc.

Hitachi America, Ltd.

Velocity Communication, Inc.

Avadhani Shridhar

Behrooz Rezvani

Sam Heidari

Raminder Singh Bajwa

Firooz Massoudi

Masoud Eskandari

Omprakash S Sarmaru

Kevin Dean Fisher

Sridhar Begur

Sigurd Schelstraete

Laurent Alloin

Jacky S Chow

Dale Smith

T R Ramesh

Hirotsugu Kojima

John Gevargiz

Rouben Toumani

Tiruvur R Ramesh

Murli Mohan Rao

Arindam Saha

Kenichi Nitta

Douglas J Gorny

Saman Behtash

Alfred K Mui

John Simons

Omprakash S Samaru

Sam Heid Ari

Sushil Agarwal

Abhijit Shah

Ying Wu

Sivannarayana Nagireddi

In general, the present invention provides an efficient usage of Far End Crosstalk (FEXT) coefficient memory in a G.fast vectoring system. According to certain aspects, embodiments of the invention provide a simple scheme for efficient management of the Discontinuous (DO) and Regular Operation (RO) FEXT coefficient memories to handle the complexity of lines joining/leaving the system in both regular and DO groups. In embodiments, by disabling the power-efficient, Discontinuous Operation, a G.fast system according to the invention first frees up the DO coefficient memory. Next, the system uses this memory as the staging area to manage joining/leaving events. Finally the system re-enables to the power-efficient Discontinuous Operation and re-populates the DO coefficient memory.

Method and apparatus for managing joining events for G.fast vectoring with discontinuous operation

A DSL system performs crosstalk cancellation using a plurality of vectoring cancellation chips that are partitioned into two or more groups based on DSL victim lines or DSL disturber lines or DSL tones. Embodiments of the invention include both single-criteria and double-criteria partitioning methods. In double-criteria embodiments, the vectoring cancellation VCE chips are first partitioned into two or more victim DSL line groups and then in each group the VCE chips are further partitioned by disturber DSL line processing. Alternately, the vectoring cancellation VCE chips are first partitioned into two or more disturber DSL line groups and then within each group further partitioned by victim DSL line processing. By partitioning the computation as described herein, the invention reduces the bandwidth and the number of links between the chips, without too much co-ordination complexity. This allows crosstalk cancellation across larger vectored groups.

System and method for partitioning DSL vector cancellation

A multi-tone modem with shared and discrete components forming a transmit path and a receive path configured to couple to a wired communication medium to communicate at least one multi-tone modulated communication channel thereon. The modem includes a multi-tone modulator component and a configurable frequency up converter component. The multi-tone modulator component is configured for multi-tone modulation and demodulation of a transmitted and received communication channel at a base band frequency range. The configurable frequency up converter component is coupled to the multi-tone modulator to selectably up convert the frequency range of the transmitted base band signal from the multi-tone modulator to that of a selected communication band and down convert received signals from the selected communication band to the base band for demodulation by the multi-tone modulator.

Method and apparatus for a multi-tone modem

A multi-tone transceiver including: a channel controller and a plurality of components forming a transmit path and a receive path. The channel controller configured to determine bit-loading for each successive symbol or tone set based on a 1noise margin target for a first subset of tones in each tone set dedicated to transport of a robust communications channel (RCC) and based on a 2noise margin target less than the 1noise margin target for remaining tones in each tone set dedicated to a standard communications channel (SCC). The plurality of components forming the transmit and receive paths are responsive to the channel controller to select for data modulated on a given tone at least one of smaller constellations and higher gain scaling levels when the given tone corresponds to an RCC tone as compared to an SCC tone, whereby the first set of tones dedicated to the RCC exhibit greater immunity to noise variations than the remaining tones dedicated to the SCC.

Method and apparatus for differentiated communication channel robustness in a multi-tone transceiver

A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters 'I, D' corresponding to block length and depth respectively. An interleaver memory buffers the communication channel. An interleaver controller controls writing to and reading from the memory of successive data elements of the communication channel with a quantity 'I' pairs of write and read pointers. Each pair or write and read pointers identifies memory locations corresponding with an input and output respectively of an associated one of &#x2018;I&#x2019; virtual first-in-first-out (&#x2018;v-FIFO&#x2019;) buffers in the memory. Control of the pointers required to read out the stored data elements in interleaved fashion is limited to shifting all pointers uniformly by one address block in each interleaver block cycle, which simplifies pointer management.

Method and apparatus for an interleaver

A bundler, un-bundler and sequencer for use in controlling and driving opposing sets of logical or physical modems to drive multiple-subscriber lines with multiple communication channels. The sequencer determines subscriber requirements such as maximum and minimum bandwidth and quality of service. The sequencer also determines bandwidth availability and status of multiple subscriber lines from which a bundle may be formed. The bundler couple to the sequencer and implement header or headerless insertion of multiple channels in round robin sequence into the X-DSL frames at data rates which correspond with subscriber requirements. The un-bundler reverses the process of the bundler and passes the appropriate packet data onto the corresponding network.

Method and apparatus for dynamic multi-line bonding in communication systems

A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and expands or contracts the tone spacing of each of a fixed number 'N' of tones accordingly by decreasing or increasing the processing interval associated with the Fourier transform of each tone set. The AFE performs digital-to-analog conversion of the multi-tone modulated communication channel at rates compatible with the processing interval of the Fourier transform module; whereby the range of frequencies spanned by the modulated tones on the subscriber line conforms to the available of frequencies on the subscriber line.

Method and apparatus for a variable bandwidth multi-protocol X-DSL transceiver

A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

Method and apparatus for a DFT/IDFT engine supporting multiple X-DSL protocols

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

Method and apparatus for a X-DSL communication processor

A method and apparatus for digital subscriber line (xDSL) communications between one or more digital signal processors (DSPs) and analog front ends (AFEs) each coupled to corresponding subscriber line(s). The apparatus transports channels of data between subscribers and the DSP(s). The apparatus includes a bus for the transport of digital data, a DSP AFE interfaces. The DSP interfaces couples the DSP to the bus. The DSP interface accepts downstream channels of digital data from the DSP and transmits packets each associated with a corresponding one of the downstream channels to the bus. Each of the packets identifies a targeted AFEs coupled to a selected one of the subscriber lines. The AFE interfaces each couple an associated one of the AFEs to the bus. Each of the AFE interfaces transmits selected packets to a selected one of the subscriber lines for the transport to the subscriber.

Method and apparatus for providing packet based and distributed xDSL communications

The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and receive path. Further flexibility is derived from an architecture which incorporates discrete and shared modules on the transmit path and the receive path. The transmit path and receive path modules are collectively controlled by control information in selected ones of the packets and operate on each channel's packets at an appropriate rate, and protocol for the channel. A digital signal processor (DSP) is disclosed which incorporates these features. The DSP exhibits a favorable form factor, and flexibility as to protocols and line codes, and numbers of channels supported.

Method and apparatus for synchronizing a packet based modem supporting multiple X-DSL protocols

A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1&plus;j i1 and r2&plus;j i2, and a twiddle factor Wn is defined as Wn&equals;e &equals;cos(2&pgr;/N)&minus;j sin(2&pgr;/N)&equals;a&plus;jb. The butterfly operation stores r1, i1, r2 and i2 in a first set of registers and stores the twiddle factor in matrix registers. The matrix-vector-multiply instruction is executed between the matrix registers and the first set of registers.

System and method for performing a fast fourier transform using a matrix-vector multiply instruction

The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.

Method and apparatus for reducing the power consumption in a

A method and apparatus for re-generating debug commands is provided comprising a source program having embedded debug commands in a first distinguishable field, and an assembler. The assembler operates on the source code extracting the embedded debug commands and associated address information from the source code while generating object code. The debug commands are stored in a command file for use during simulation. A simulator executes the assembled object code in conjunction with a debugger which executes the stored debug commands as designated during the execution cycle. Upon the termination of a simulation run and the subsequent modification of the source program, the debug commands are automatically re-generated with correct addresses as determined during the subsequent assembly. When the edited source file is loaded, the break-points are cleared and a new command file is executed to insure that the break-points are relocated to the correct source lines. The execution of the embedded debug commands can be enabled or disabled by means of a command line option, so when the debugging is complete, the debug information will not be outputted.

Embedded debug commands in a source file

A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All systems providing this capability must know when to refetch the first loop instruction at the end of a repeat. To do this, the present invention adds a repeat bit to the processor's instruction set. This bit is set by the assembler/compiler that generates the executable code fragment comprising the repeat loop. Where the repeat loop includes plural instructions, the assembler sets the repeat bit of the penultimate loop instruction. As each loop instruction is fetched, decoded and executed, the decoder detects the repeat bit and passes it to loop control circuitry. If the code fragment has not been iterated N times and the repeat bit is set, the program counter (PC) is loaded with the address of the first repeat loop instruction, which is refetched. Otherwise, the PC is incremented and the next instruction is fetched. Where the repeat loop has a single instruction, a nop instruction must be added after the instruction to be repeated. Two systems and methods for maintaining the repeat count are disclosed. The first requires a decrementor that decrements the repeat count from N each time the loop is iterated. Another replaces the decrementor with the PC incrementor, which increments the repeat counter from -N or -(N-1).

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Santa Clara, CA, United States of America

Avadhani Shridhar