Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hiatchi, Ltd.

Atsushi Hiraiwa

Satoshi Sakai

Isamu Asano

Masakazu Sagawa

Yoshitaka Tadaki

Shinji Shimizu

Toshihiro Sekiguchi

Jun Murata

Mitsuaki Horiuchi

Jun Sugiura

Hidetsugu Ogishi

Hiroko Kaneko

Masami Ozawa

Satoshi Yamamoto

Dai Ishikawa

Eiji Takeda

ShinIchiro Kimura

Takayuki Sasaki

Tokuo Kure

Masahiro Moniwa

Toru Kaga

Motoshige Igarashi

Naozumi Morino

Masao Sugiyama

Dai Hisamoto

Hiroshi Yanagita

Toshiaki Ito

Haruhiko Tanaka

Kazutoshi Oku

Shinichi Watarai

Shuji Ikeda

Takashi Kobayashi

Norio Suzuki

Yasuo Wada

Yasuko Yoshida

Shinpei Iijima

Jiro Yugami

Shigeru Takahashi

Yoshihiro Ikeda

Takayuki Kanda

Shinichi Horibe

Shimpei Iijima

Takashi Hashimoto

Toshiyuki Mine

Kenichi Kawabata

Keizo Suzuki

Kenji Yasuda

Kazuyoshi Oshima

Shinichiro Umemura

Kazuo Takeda

Osamu Tsuchiya

Yoshifumi Kawamoto

Nobuyoshi Kobayashi

Hideo Sunami

Kozo Watanabe

Sadayuki Okudaira

Kenko Uchida

Satoru Ito

Ken Ninomiya

Shigeru Nishimatsu

Kiichiro Mukai

Takashi Nishida

Kiyonori Ohyu

Seiki Harada

Katsuhisa Usami

Shin-ichi Muramatsu

Ryuichi Izawa

Mitsuo Nanba

Ryoichi Furukawa

Seiichi Iwata

Hidetsugu Ishida

Yasuo Igura

Takeo Yoshimi

Akemi Hamada

There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Semiconductor device having a plurality of shallow wells

Semiconductor device

After silicon oxide film () is formed on the surface of a semiconductor substrate (), the silicon oxide film () in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film () is formed on the semiconductor substrate (). Consequently, two kinds of gate insulation films, namely, a gate insulation film () comprised of stacked film of high dielectric constant insulation film () and silicon oxide film () and gate insulation film () comprised of the high dielectric constant insulation film () are formed on the semiconductor substrate ().

Semiconductor integrated circuit device and manufacturing method thereof

According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

Method for fabricating semiconductor devices

A method of manufacturing a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film so as to form a silicon oxynitride film, exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film in order to form a silicon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.

Method of manufacturing a semiconductor integrated circuit device

After forming a silicon oxide filmon the surface of a region A of a semiconductor substratea high dielectric constant insulating filma silicon film, a silicon oxide filmare successively deposited over the semiconductor substrateand they are patterned to leave the silicon oxide filmin regions for forming gate electrodes. Then, after fabricating silicon filmsandby using the patterned silicon oxide filmas a mask, when removing the silicon oxide filmetching is performed under the condition where the etching selectivity of the silicon oxide filmto the high dielectric constant insulating filmbecomes large, thereby leaving the high dielectric constant insulating filmalso to portions below the end of the gate electrodes (). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.

Semiconductor integrated circuit device and method for fabricating the same

A protection film is formed on a silicon oxide film formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

A method of manufacturing a semiconductor integrated circuit device includes steps of forming a silicon oxide film as thin as 5 nm or less on the surfaces of p-type wells and n-type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film to form a silicon oxynitride film, and exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film to form a silcon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.

A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.

Semiconductor integrated circuit device having switching misfet and capacitor element and method of producing the same, including wiring therefor and method of producing such wiring

Growing community of inventors

Higashimurayama, Japan

Atsushi Hiraiwa