Matsushita Electric Industrial Co., Ltd.

Kabushiki Kaisha Ishida Koki Seisakusho

Atsushi Fujiwara

Toshio Yamada

Akinori Shibayama

Shin Hashimoto

Isao Miyanaga

Yasushi Okuda

Yoshirou Nakata

Yukiharu Uraoka

Kenzou Hatada

Michihiro Inoue

Yoshiro Nakata

Masanori Matsuura

Kenji Misumi

Kazuhiro Matsuyama

Toshio Nishimoto

Hiroyuki Yamauchi

Masashi Agata

Shunichi Iwanari

Naohisa Tatsukawa

A writing operation selecting circuit is provided for selecting a temporary writing operation having a prescribed writing time for a memory cell transistor element and an additional writing operation for the memory cell transistor element. A writing time control circuit is provided for controlling an additional writing operation time by an output signal of the writing operation selecting circuit.

Semiconductor nonvolatile storage device

In a nonvolatile memory device, wherein, for example, data '1' is electrically charged, while data '0' is not electrically charged, and memory cells susceptible to charge loss are included, when data in the arrayis count value of &#x201c;1&#x201d;&#x3e;count value of &#x201c;0&#x201d;, write data is converted to thereby make &#x201c;1&#x201d; to &#x201c;0&#x201d; and &#x201c;0&#x201d; to &#x201c;1&#x201d;, leading to number of &#x201c;1&#x201d;&#x3c;number of &#x201c;0&#x201d;, so that a statistical reliability of the data in the arrayis improved. The data, which is converted and written, is converted in its polarity prior to the conversion when it is read.

Semiconductor nonvolatile memory device

The semiconductor memory device, provided with a secondary regular memory region for storing a rewrite program and the like in addition to a primary regular memory region for storing data, includes a spare block decoder for enabling selection of a spare memory block and a register section for holding a signal that activates the spare block decoder. Whether the spare memory block is used as the secondary regular memory region or as a spare memory block for redundancy defect replacement is controlled with the signal held in the register section. In this way, the secondary regular memory region is provided without increasing the area.

Semiconductor memory device

A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method

Semiconductor wafer package, method and apparatus for connecting testing

The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously. Consequently, there can be provided a semiconductor testing apparatus which realizes the reduction in price and the increase in number of the semiconductor integrated circuits tested simultaneously, thereby significantly reducing the cost of testing the semiconductor integrated circuits.

Semiconductor testing apparatus, semiconductor testing circuit chip, and

In a circuit, a resistance element is interposed between a positive power supply line (external power supply voltage level VCC) and an output node. To feedback an output potential, there is disposed an N-type MOSFET of which gate is connected to the output node and of which source is connected to the earth line (earth potential VSS) in the circuit. Another three N-type MOSFETs which are so connected in series to one another as to form a MOS diode, are interposed between the drain of the feedback N-type MOSFET and the output node. The earth line also serves as a reference potential line for the potential of the output node. Variations of the threshold voltages of the MOSFETs due to temperature variations are compensated. This restrains the output potential from varying.

Reference potential generating circuit and semiconductor integrated

A semiconductor memory device with a redundancy configuration with a higher corrective efficiency is disclosed. Primary memory cell arrays 3a, 3b, and 3c are arranged in memory cell blocks a, b, and c. spare memory cell arrays 2b and 2c are arranged in the memory cell blocks b and c. When the address of an address signal supplied agrees with the address of a defective primary memory cell in one memory cell block, a spare memory cell in the other memory cell block selected for such a defective memory cell. Even if a word line of the primary and a word line of the spare memory cells are selected at the same time, it is possible to access read data in a nondestructive manner. This achieves a high-speed word line activation as well as an improved corrective efficiency. The provision of a row decoder that connects a primary word line to a spare word line with a shared decode line prevents the increase of the area of memory chips due to the arrangement of a Spare memory cell.

Redundancy semiconductor memory device which utilizes spare memory cells

A power circuit for a semiconductor apparatus comprising an internal power voltage generating circuit generating an internal power voltage, an external power voltage detecting circuit, a power voltage switching circuit switching the internal power voltage to the external power voltage in response to the output of the external power voltage detecting circuit, and a switching signal setting circuit. The output of the power voltage switching circuit is the internal power voltage when power is first applied to the semiconductor device. The switching signal setting circuit provides the correct power voltage switching signals quickly to the power voltage switching circuit when power is applied and the external power voltage is not inputted to the apparatus at the early stage of power application.

Power circuit for a semiconductor apparatus

In a MOS integrated circuit is provided a first differential amplifying circuit for receiving complementary sets of input data at the gates of its two p-channel MOS transistors and for transmitting complementary sets of internal data. There is also provided a second differential amplifying circuit for receiving the complementary sets of internal data at the gates of its two n-channel MOS transistors and for transmitting complementary sets of output data. This realizes high-speed data transmission in which data transmission speed is independent of the generation of a clock signal. By preventing the flow of current from a power supply terminal to a ground terminal, a differential transmission circuit which consumes reduced current can be obtained.

Differential transmission circuit

A method is provided for testing a semiconductor integrated circuit including a main circuit, a self testing circuit for testing at least one part of the functions of the main circuit, and a test result output circuit having at least one light emitting device for outputting results from the self testing circuit in the form of light. The method includes the steps of inputting a test start to the self testing circuit so as to initiate operation of the self testing circuit; detecting light emitted from the light emitting device with an optical system, the light being emitted based on the test results from the self testing circuit; and obtaining the test results based on the light detection.

Method for testing a semiconductor integrated circuit having self

A semiconductor integrated circuit has a main circuit (1), a self testing circuit (2) for testing the main circuit (1), a test start signal detection circuit (5) having at least one light sensitive device for detecting a test start signal in the form of light, and a test result output circuit (4) having at least one light emitting device for outputting test results from the self testing circuit (2) in the form of light. A drastic reduction in test time is accomplished by applying the test start signal in a non-contacting manner to the semiconductor integrated circuit so as to activate the self testing circuit. Furthermore, the test result is output to the outside of the semiconductor integrated circuit without having to provide electrical connections, and the simultaneous testing of a greater number of semiconductor integrated circuits as formed on the same wafer can be accomplished.

Growing community of inventors

Kyoto, Japan

Atsushi Fujiwara