Nec Corporation

Atsuki Ono

Kiyotaka Imai

Nobuaki Hamanaka

Katsuhiko Fukasaku

The relationship between the difference between design and measured values of the gate length of a gate electrode of a transistor and the dose of an impurity to be injected into SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values is formulated. The gate length of the gate electrode which is produced by photolithography and etching process is measured. The dose of the impurity to be injected into the SD extension regions or the pocket regions is adjusted to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.

Method of forming S/D extension regions and pocket regions based on formulated relationship between design and measured values of gate length

A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

Method for manufacturing a semiconductor device having a silicide layer

An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the n-channel type field effect transistor is thinner than the boron-doped gate electrode of the p-channel type field effect transistor so that the arsenic and the boron are appropriately diffused in the gate electrodes during a rapid annealing.

Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof

Method of forming MOS transistor

A section separator region is formed in a semiconductor substrate in which a p-type well region has been formed, to separate the substrate into an I/O section and a core section. An oxide film and a plysilicon film are form at the I/O section, and pre-formation treatment is carried out. Then, an oxide film is formed over the exposed surface by the thermal oxidization. A metal film is formed on the oxide film. The metal film on the I/O section is moved. The polysilicon film and the metal film are patterned to be gate electrodes. Then, ion implantation is carried out to implant impurity into the exposed surface to form source/drain regions corresponding to the gate electrodes respectively.

Method of manufacturing semiconductor device

A process for preparing a semiconductor which is capable of implanting indium effectively during the process of forming a gate insulation film with different levels of thickness includes a 1 step of forming a 1 resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed thereon to form a P-well region before forming a 1 N-channel region made of components other than indium on the P-well region, a 2 step of removing the 1 resist mask before forming a 1 gate insulation film on the surface of the substrate, a 3 step of forming a 2 resist mask on the predetermined region except the 1 N-channel region after forming the 1 gate insulation film, and removing partially the 1 gate insulation film, a 4 step of forming a P-well region inside the 1 gate insulation film partially removed region before forming a 2 N-channel region containing indium on this P-well region, and a 5 step of removing the 2 resist mask before forming a 2 gate insulation film on the surface of the 2 N-channel region.

Production of a semiconductor device having a P-well

In manufacturing a MOS field effect transistor having a gate oxide film with a thickness of 3 nm or less, a deposition treatment or the like is performed under the condition that the substrate temperature is 650 to 770&deg; C., and thereafter an annealing treatment is carried out under the condition that the substrate temperature is 900 to 1100&deg; C.

After a source-drain region is formed, fluorine,is ion-implanted into the entire surface of a substrate and thereafter a heat treatment is conducted, for example, at 600 to 800&deg; C. Through this heat treatment, the dangling binds and the Si&mdash;H bonds in the channel regions,are substituted by the Si&mdash;F bonds, which prevents the generation of the negative bias temperature instability effect in a MOSFET.

Manufacturing method of semiconductor device

Semiconductor device having field effect transistors different in

A method of manufacturing a semiconductor device includes the step of forming a gate electrode on a semiconductor substrate via a gate insulating film and the step of forming a first insulating film on side surfaces of the gate electrode and an upper surface of the semiconductor substrate. Also the method includes the step of forming a second insulating film on the first insulating film and the step of etching back the first and second insulating films to form side walls of the gate electrode each of which includes layers of the first and second insulating films. The method includes the step of etching the first insulating films of the side walls to remain a part of the first insulating film layers.

Semiconductor device having plural air gaps for decreasing parasitic

A side-wall film of a gate electrode is fabricated as a two-layer structure including an underlying thin silicon nitride film and a relatively thick silicon oxide film. The silicon nitride film covers and protects the edge of the gate oxide film against formation of a gate bird's beak at the edge of the gate oxide film. The side-wall contacts with the silicon substrate substantially at the thick silicon oxide film of the side-wall, which prevents formation of a carrier trap area adjacent to the channel area. The bottom of the side-wall may be a nitride-doped silicon oxide instead.

Method for manufacturing a MOSFET having a side-wall film formed through

Elevated source and drain regions epitaxially grown on both sides of a gate structure cause a dopant impurity to form an extremely shallow p-n junctions in a semiconductor substrate so as to prevent a field effect transistor from a short channel effect, and side wall spacers include pad layers of silicon nitride and spacer layers of silicon oxide formed on the pad layers so that the elevated source and drain regions form boundaries to the pad layers without a facet and a silicon layer on the spacer layers.

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Tokyo, Japan

Atsuki Ono