Toshiba Memory Corporation

Asuka Kaneda

Yasuhiro Shiino

Koki Ueno

A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.

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Yokohama Kanagawa, Japan

Asuka Kaneda