Sun Microsystems, Inc.

Ashutosh K Das

Sridhar Narayanan

Edgardo F Klass

Chaim Nmi Amir

Anup S Mehta

A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes a same-gate symmetrical design and reverse polarity control signals to overcome disadvantages of prior circuits while accommodating increasing circuit speeds. The circuit employs all NAND gates on the select lines controlling multiplexer transmission gates rather than NAND gates and a NOR gate. The design may also be implemented using AND gates. In addition to using a NAND gate where prior designs use a NOR gate, the polarity of the flip-flop output which drives the additional NAND gate is inverted, and the polarity of the input to the transmission gate driven by the additional NAND gate is also inverted. The circuit thus provides a symmetric design using the same NAND logic gates on all select lines while preserving functionality of the n-to-1 multiplexer. The symmetry of the design avoids problems which are inherent to prior asymmetrical designs is having NAND gates and a NOR gate, such as uneven delays on the select lines which can result in a short circuit for brief periods of time and the additional design effort required to overcome loading on NOR gate inputs resulting from NOR gates having increased area.

Circuit for avoiding contention in one-hot or one-cold multiplexer designs

A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

Edge-triggered dual-rail dynamic flip-flop with an enhanced self-shut-off mechanism

A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or ground (i.e., shorted to a logical 1 or logical 0) and the precise location of the short. Circuitry in the flip-flops (or other sequential elements) forming the scan chain allows the scan output of each flip-flop to be set or reset by switching a scan enable signal between logic states. If there is a fault in the scan chain where a node is stuck at a logical 1, then resetting the scan outputs of the flip-flops to 0 and clocking the flip-flops will result in a logical 1 being output from the last flip-flop after a number of clock pulses. The number of clock pulses indicates the position of the flip-flop in the scan chain which is associated with the fault. A similar technique detects a stuck-at-0 fault by setting the flip-flops to 1. In a preferred embodiment, each adjacent pair of flipflops in the chain consists of a flip-flop whose scan output can be reset to a 0 and a flip-flop whose scan output can be set to a 1.

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Sunnyvale, CA, United States of America

Ashutosh K Das