Adeia Semiconductor Bonding Technologies Inc.

National Semiconductor Corporation

Texas Instruments Corporation

Eastman-kodak Company

Adeia Semiconductor Technologies LLC

Ashok S Prabhu

Anindya Poddar

Zhuowen Sun

Wael Zohni

Luu Thanh Nguyen

Abiola A Awujoola

Willmar E Subido

Rajesh Katkar

Jaime A Bayan

Hau Thanh Nguyen

Belgacem Haba

Min Tao

Hoki Kim

Shaw Wei Lee

Hem P Takiar

Yi Yan

Nikhil Vishwanath Kelkar

Makoto Yoshino

Javier A DeLaCruz

Liang Wang

Reynaldo Co

Alexander H Owens

Genki Yano

Chan Peng Yeen

Sadanand R Patil

Shoichi Iriguchi

Christopher Lattin

Sean Moran

Santhiran S/o Nadarajah

Hiroyuki Sada

Dibyajat Mishra

Tomoko Noguchi

Hasfiza Ramley

Chan Chee Ling

Cyprian Emeka Uzoh

Peter B Johnson

Rajeev Dinkar Joshi

Hong Shen

Mutsumi Masumoto

Ken Pham

Woochan Kim

Makoto Shibuya

Nghia Thuc Tu

Kengo Aoya

Scott P McGrath

Masamitsu Matsuura

Inderjit Singh

Vijaylaxmi Gumaste Khanolkar

Mahmud Halim Chowdhury

Sangil Lee

Christopher G Quentin

Fred Drummond

Ming Li

Jamie A Bayan

Lye Meng Kong

Santhiran S O Nadarajah

Edgar Dorotyao Balidoy

Abiola Awujoola

Willmar Subido

Kurt Edward Sincerbox

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Wire bond wires for interference shielding

A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

Semiconductor device package with thermal pad

In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

Flip chip packaged devices with thermal pad

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Bump bond structure for enhanced electromigration performance

An electronic device () includes a substrate () and an integrated circuit () provided on the substrate () having a surface facing away from the substrate (). An insulating layer () extends over the substrate () and around the integrated circuit () to define an interface () between the insulating layer () and the integrated circuit (). An electrically conductive via () is provided on the surface of the integrated circuit (). An insulating material () extends over the via () and includes an opening () exposing a portion of the via (). A repassivation member () extends over the insulating layer () and has a surface () aligned with the interface (). An electrically conductive redistribution member () is electrically connected to the via () and extends over the repassivation member () into contact with the insulating layer ().

Fan-out electronic device

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

Integrated circuit backside metallization

In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 &#x3bc;m on a surface of the copper corrosion inhibitor layer.

Copper passivation

Apparatus to form a transformer, an inductor, a capacitor or other passive electronic component, with patterned conductive features in a lamination structure, and one or more ferrite sheets or other magnetic core structures attached to the lamination structure via one or more inkjet printed magnetic adhesive layers that join the magnetic core structure or structures to the lamination structure.

Additive deposition low temperature curable magnetic interconnecting layer for power components integration

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Embedded wire bond wires

Dies-on-package devices and methods therefor are disclosed. In a dies-on-package device, a first IC die is surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region with respect to the first IC die. A molding layer is formed over the upper surface of the package substrate, around sidewall surfaces of the first IC die, and around bases and shafts of the conductive lines. A plurality of second IC dies is located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. The plurality of second IC dies are respectively coupled to the sets of the conductive lines in middle third portions respectively of the plurality of second IC dies for corresponding fan-in regions thereof.

Dies-on-package devices and methods therefor

Growing community of inventors

San Jose, CA, United States of America

Ashok S Prabhu