Fairchild Semiconductor Corporation

Fairchild Semiconductor Corporatiion

Ashok Challa

Steven Paul Sapp

Joseph Andrew Yedinak

Daniel S Calafut

Dean E Probst

Christopher Boguslaw Kocon

Nathan Lawrence Kraft

Hamza Yilmaz

Bruce Douglas Marchant

Daniel Marvin Kinzer

Izak Bencuya

Brian Sze-Ki Mo

Alan Elbanhawy

Peter H Wilson

Babak S Sani

Thomas E Grebs

Gary M Dolny

Rodney S Ridley

James J Murphy

Paul Thorup

Becky Losee

Robert Herrick

Ihsiu Ho

Gordon K Madson

Jaegil Lee

Hocheol Jang

Debra S Woolsey

Jinyoung Jung

Adrian Mikolajczak

Chanho Park

Suku Kim

Dan Kinzer

Mark Larsen

Ritu Sodhi

Tirthajyoti Sarkar

Dan Calafut

Seokjin Jo

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Trench-based power semiconductor devices with increased breakdown voltage characteristics

In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

Junction-less insulated gate current limiter device

In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region.

Direct-drain trench FET with source and drain isolation

In one general aspsect, a semiconductor device can include at least a first device region and a second device region disposed at a surface of a semiconductor region where the second device region is adjacent to the first device region and spaced apart from the first device region. That semiconductor device can include a connection region disposed between the first device region and the second device region, and a trench extending into the semiconductor region and at least extending from the first device region, through the connection region, and to the second device region. The semiconductor device can include a dielectric layer lining opposing sidewalls of the trench, an electrode disposed in the trench, and a conductive trace disposed over a portion of the trench in the connection region and electrically coupled to a portion of the electrode disposed in the connection region.

A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

Methods related to power semiconductor devices with thick bottom oxide layers

In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.

Shielded gate field effect transistors

In one general aspect, a termination structure can include a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type where the plurality of pillars define a plurality of concentric rings surrounding an active area of a semiconductor device. The termination structure can include a conductive field plate where the plurality of pillars includes a first pillar coupled to the conductive field plate. The termination structure can include a dielectric layer where the plurality of pillars include a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars.

Power semiconductor devices having termination structures

A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches includes a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

Field effect transistor with gated and non-gated trenches

A metal-oxide-semiconductor field effect transistor (MOSFET) includes a substrate, the substrate being heavily doped and of a first conductivity type, a substrate cap region disposed on the substrate, the substrate cap region being heavily doped and of the first conductivity type and a body region disposed on the substrate cap region, the body region being lightly doped and of a second conductivity type. The MOSFET also includes a trench extending into the body region, a source region of the first conductivity type disposed in the body region and in contact with an upper portion of a sidewall of the trench and an out-diffusion region of the first conductivity type formed such that a spacing between the source region and the out-diffusion region defines a channel region of the MOSFET extending along the sidewall of the trench.

FET device having ultra-low on-resistance and low gate charge

In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench.

MOSFET device with thick trench bottom oxide

Field effect transistor with source, heavy body region and shielded gate

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Sandy, UT, United States of America

Ashok Challa