Texas Instruments Corporation

Asad Mahmood Haider

Qhalid Fareed

Byron Lovell Williams

Kelly Jay Taylor

Satyavolu Srinivas Papa Rao

Jungwoo Joh

Licheng Marshal Han

Ed Burke

Scott Robert Summerfelt

Thomas Dyer Bonifield

Bhaskar Srinivasan

Haowen Bu

Richard L Guldi

Ricky A Jackson

Deepak Arabagatte Ramappa

Brian Goodlin

William Robert Morrison

Scott Kelly Montgomery

John Britton Robbins

Alfred J Griffin, Jr

ChangFeng F Xia

Frank D Poag

Thomas W Winter

James Wayne Klawinsky

Arunthathi Sivasothy

Gregory D Winterton

Hidenori Kawata

Roger Charles McDermott

Changfeng Xia

A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of &#x3c;10 &#x212b; and (ii) a pit density for pits greater than (&#x3e;) 2 nm deep less than (&#x3c;) 10 pits per square &#x3bc;m with an average pit diameter less than (&#x3c;) 0.05 &#x3bc;m.

Method of fabricating non-etch gas cooled epitaxial stack for group IIIA-N devices

Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.

Process for forming PZT or PLZT thinfilms with low defectivity

An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Integrated circuit with micro inductor and micro transformer with magnetic core

A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Buffer stack for group IIIA-N devices

A process of forming an integrated circuit containing a piezoelectric thin film by forming a sol gel layer, drying in at least 1 percent relative humidity, baking starting between 100 and 225&#xb0; C. increasing to between 275 and 425&#xb0; C. over at least 2 minutes, and forming the piezoelectric thin film by baking the sol gel layer between 250 and 350&#xb0; C. for at least 20 seconds, annealing between 650 and 750&#xb0; C. for at least 60 seconds in an oxidizing ambient pressure between 700 and 1000 torr and a flow rate between 3 and 7 slm, followed by annealing between 650 and 750&#xb0; C. for at least 20 seconds in a pressure between 4 and 10 torr and a flow rate of at least 5 slm, followed by ramping down the temperature.

Piezoelectric thin film process

A microelectronic device with a ferroelectric layer is formed using an MOCVD tool. A substrate is disposed on a susceptor heated to 600&#xb0; C. to 650&#xb0; C. A first carrier gas is flowed into a manifold to combine with a plurality of metal organic precursors. The first carrier gas, the metal organic precursors, and a second carrier gas, are flowed through a vaporizer into a chamber of the MOCVD tool, over the substrate. A ratio of a flow rate of the first carrier gas to a flow rate of the metal organic precursors is 250 sccm/milliliter/minute to 500 sccm/milliliter/minute. A ratio of a flow rate of the second carrier gas to a flow rate of the metal organic precursors is 700 sccm/milliliter/minute to 1500 sccm/milliliter/minute. An oxidizing gas is flowed into the chamber over the substrate. The metal organic precursors and the oxidizing gas react to form the ferroelectric layer.

Process to enable ferroelectric layers on large area substrates

A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750&#xb0; C.

FET dielectric reliability enhancement

An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.

Integrated circuit structure with capacitor and resistor and method for forming

A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.

Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level

The invention provides a method of fabricating a semiconductive device []. In this embodiment, the method comprises depositing a hydrocarbon layer [] over a semiconductive substrate, forming an interconnect structure [] within the hydrocarbon layer [], and removing the hydrocarbon layer [] by sublimation.

Semiconductive device fabricated using subliming materials to form interlevel dielectrics

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Plano, TX, United States of America

Asad Mahmood Haider