Applied Materials, Inc.

National University of Singapore

Arvind Sundarrajan

Guan Huei See

Sriskantharajah Thirunavukarasu

Prayudi Lianto

Peijun Ding

Peng Suo

Srinivas D Nemani

John C Forster

Bo Zheng

Xinyu Fu

Yu Gu

Praburam Gopalraja

Ellie Y Yieh

Xianmin Tang

Eng Sheng Peh

Jen Sern Lew

Dinesh Saigal

Avinash Avula

Zheng Xu

Jianming Fu

Fusen E Chen

Roderick Craig Mosely

Michael A Miller

Murali K Narasimhan

Rong Tao

Suraj Rengarajan

Daniel Clarence Lubben

Ying W Wang

James H Tsung

Chang Bum Yong

Darryl Angelo

Mei Yin Chang

Steven Verhaverbeke

Eric J Bergman

Barry Lee Chin

Tza-Jing Gung

Han-Wen Chen

Roman Gouk

Prerna Sonthalia Goradia

Edward P Hammond

Glen T Mori

Chin Hock Toh

Ranga Rao Arnepalli

Richard Hong

Karthik Elumalai

Mark A Perrin

Zongbin Wang

Andrew S Gillard

Mohamed Rafi

Nitin K Ingle

Michael Robert Rice

Hua Chung

Robert Jan Visser

John Leonard Sudijono

James S Papanu

Pravin K Narwankar

Suketu Arun Parikh

John Lee Klocke

Seshadri Ramaswami

Upendra V Ummethala

Kyuil Cho

Michael C Kutney

Andrew W Yeoh

Yueh Sheng Ow

Boyi Fu

Jick M Yu

Bharat Bhushan

Colin Costano Neikirk

Jie Zeng

Siew Kit Hoi

Marvin L Bernt

Tse-Yong Yao

Sameer Deshpande

Joe Griffith Cruz

Tuck Foong Koh

Jiao Song

Victor Pushparaj

Ilyoung R Hong

Ginetto Addiego

Ashish Pal

Charles Sharbono

Jun-Liang Su

Vicknesh Sahmuganathan

Nuno Yen-Chu Chen

Yen-Chu Yang

Fang Jie Lim

Sam Lee

Martinus Maria Berkens

James Van Gogh

Cheng Sun

Felix Deng

Karrthik Parathithasan

Loke Yuen Wong

El Mehdi Bazizi

Chin Wei Tan

Gaurav Mehta

Linh Thanh

Yue Cui

Xundong Dai

Ramesh Chidambaram

A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.

Self-aligned wide backside power rail contacts to multiple transistor sources

Methods and apparatus for processing a substrate are provided herein. For example, methods for enhancing surface hydrophilicity on a substrate comprise a) supplying, using a remote plasma source, water vapor plasma to a processing volume of a plasma processing chamber to treat a bonding surface of the substrate, b) supplying at least one of microwave power or RF power at a frequency from about 1 kHz to 10 GHz and a power from about 1 kW to 10 kW to the plasma processing chamber to maintain the water vapor plasma within the processing volume during operation, and c) continuing a) and b) until the bonding surface of the substrate has a hydrophilic contact angle of less than 10°.

Water vapor plasma to enhance surface hydrophilicity

A method of thinning a die engaged with a substrate is disclosed, utilizing dry etching of a top surface of the die with a plasma comprising fluorine to selectively remove the top surface of the die relative to a top surface of the substrate.

Silicon (Si) dry etch for die-to-wafer thinning

The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.

Methods of TSV formation for advanced packaging

Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a surface of a substrate for determining in-situ ESE data therefrom during substrate processing, measuring a change of phase and amplitude in determined in-situ ESE data, and determining various aspects of the surface of the substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from a measured change of phase and amplitude in the in-situ ESE data.

Methods and apparatus for processing a substrate

Methods of curing a polymer layer on a substrate using variable microwave frequency are provided herein. In some embodiments, methods of curing a polymer layer on a substrate using variable microwave frequency include (a) forming a first thin-film polymer layer on a substrate, the first thin-film polymer layer including at least one first base dielectric material and at least one microwave tunable material, (b) applying a variable frequency microwave energy to the substrate and the first thin-film polymer layer to heat the substrate and the first thin-film polymer layer to a first temperature, and (c) adjusting the variable frequency microwave energy applied to the substrate and the first thin-film polymer layer to tune at least one material property of the first thin-film polymer layer.

Methods for forming microwave tunable composited thin-film dielectric layer

Methods and apparatus for processing a first substrate and a second substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a first surface of a first substrate and a second surface of a second substrate, which is different than the first substrate, determining in-situ ESE data from each of the first surface and the second surface during processing of the first substrate and the second substrate, measuring a change of phase and amplitude in determined in-situ ESE data, and determining one or more parameters of the first surface of the first substrate and the second surface of the second substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from the measured change of phase and amplitude in the in-situ ESE data.

A method of forming a magnetic core on a substrate having a stacked inductor coil includes etching a plurality of polymer layers to form at least one feature through the plurality of polymer layers, wherein the at least one feature is disposed within a central region of a stacked inductor coil formed on the substrate; and depositing a magnetic material within the at least one feature.

Semiconductor substrate having magnetic core inductor

Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 &#x3bc;m l/s fine pitch patterning.

Methods and apparatus for controlling warpage in wafer level packaging processes

Methods of forming through-silicon vias in substrates for advanced packaging

Method of forming a magnetic core on a substrate

Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.

Methods for bonding substrates

Embodiments of substrate transfer apparatus are provided herein. In some embodiments, an apparatus for storing and transporting at least one substrate in a vacuum includes a carrying case for storing one or more substrates, wherein the carrying case includes a vacuum port and a plurality of holders to hold one or more substrates within an inner volume of the carrying case; and a vacuum source in fluid connection with the carrying case via the vacuum port.

Substrate vacuum transport and storage apparatus

Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.

Methods and apparatus for backside via reveal processing

Growing community of inventors

Singapore, Singapore

Arvind Sundarrajan