International Business Machines Corporation

Globalfoundries Inc.

Texas Instruments Corporation

Adeia Semiconductor Bonding Technologies Inc.

Cornell Research Foundation Inc.

Globalfoundries U.S. 2 LLC

Teradata Us, Inc.

Arvind Kumar

Anthony I Chou

Shreesh Narasimha

Chung-Hsun Lin

Claude Ortolland

Renee Tong Mo

Joshua M Rubin

Brian Joseph Greene

Carl John Radens

Ramachandra Divakaruni

Judson Robert Holt

Dan Mihai Mocuta

Kangguo Cheng

Bruce Bennett Doris

Ali Khakifirooz

Takashi Ando

Shom Ponoth

Andres Bryant

Robert Russell Robison

Dirk Pfeiffer

Babar Ali Khan

Ahmet Serkan Ozcan

Balasubramanian S Haran

Sandip Tiwari

Mark C Lamorey

Devendra K Sadana

Lawrence Alfred Clevenger

Ning Li

Jeffrey W Sleight

Vijay Narayanan

Toshiaki Kirihata

Joel Pereira De Souza

Subramanian Srikanteswara Iyer

Martin Michael Frank

Igor Arsovski

Robert H Dennard

Xiao Hu Liu

Vamsi Krishna Paruchuri

Kamal Kumar Sikka

Yun Seog Lee

Jean-Olivier Plouchart

Henry K Utomo

Vijay Kumar Ananthapur Bache

Nivo Rovedo

Suparna Bhattacharya

Troy Lawrence Graves-Abe

Charles Edwin Cox

Harald Huels

Daniel George Berger

Vijay Ekambaram

Dechao Guo

Mukta G Farooq

Sharathchandra UmapathiRao Pankanti

Charles Leon Arvin

Wilfried Haensch

Ravi Nair

Pranita Kulkarni

Pranita Kerber

Peilin Song

Jon Alfred Casey

Viorel C Ontalus

Steven Lorenz Wright

Gregory Gower Freeman

Padmanabha Venkatagiri Seshadri

Paul S Chang

Edward P Maciejewski

Timothy James McArdle

Swagath Venkataramani

Christopher D Sheraw

Robert J Miller

Mark William Kapfhammer

Huiling Shang

Dinesh Gupta

Bhupesh Chandra

John Ulrich Knickerbocker

Timothy Joseph Chainer

Katherine Lynn Saenger

Michael Patrick Chudzik

Leland Chang

Bing Dang

Jeng-Bang Yau

Amlan Majumdar

Todd Edward Takken

Sami Rosenblatt

Unoh Kwon

Raghuveer Prasad Nagar

Vijayalakshmi Srinivasan

Markus Brink

Hussein Ibrahim Hanafi

Matthew R Wordeman

Leathen Shi

Wiren Dale Becker

Qianwen Chen

Brian L Ji

Vivekananda P Adiga

Jared Barney Hertzberg

Shawn Peter Fetterolf

Murshed Chowdhury

Mounir Meghelli

Pritish Narayanan

An exemplary apparatus includes a substrate; a plurality of chips mounted onto the substrate; a plurality of cold plates corresponding to the plurality of chips; means for pressing each of the cold plates toward a corresponding one of the chips; means for delivering coolant flow to the cold plates; and means for adjusting the cooling power of the plurality of cold plates, responsive to at least one sensed parameter of the plurality of chips.

Heterogeneous integrated multi-chip cooler module

A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

Back-side memory element with local memory select transistor

Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data/information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.

Interconnection structures for high bandwidth data transfer

A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

Multichannel memory to augment local memory

A multichip module with a vertical stack of a logic chip, a translator chip, and at least one memory chip. The multichip module includes a logic chip, a translator chip over and vertically connecting to the logic chip, and at least one memory chip above and vertically connecting to the translator chip where the translator chip is one of a chip with active devices or a passive chip.

Memory and logic chip stack with a translator chip

An obfuscation circuit relies on a tamper-resistant nonvolatile memory which encodes a trusted Boolean function. The Boolean function is used to enable several operations relating to circuit obfuscation, including obfuscation of logic circuitry, obfuscation of operand data, and release of IP blocks. The tamper-resistant nonvolatile memory is part of a trusted integrated circuit structure, i.e., one fabricated by a trusted foundry, separate from another integrated circuit structure which contains the various operational logic circuits of the design and is fabricated by an untrusted foundry. The Boolean function is encoded based on a look-up table implemented as a cascaded multiplexer circuit. Multiple obfuscation functions can be so encoded. The obfuscation functions may be reprogrammed using a protocol that relies on symmetric keys, one of which is stored in the tamper-resistant nonvolatile memory.

Tamper resistant obfuscation circuit

One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including 'die first' and 'die last' methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.

Precision thin electronics handling integration

A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

Tamper-resistant circuit, back-end of the line memory and physical unclonable function for supply chain protection

A technique relates to biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions. The control system reinforces the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition. The control system records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.

Secure chip identification using resistive processing unit as a physically unclonable function

A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

Lithium drifted thin film transistors for neuromorphic computing

Various embodiments are provided for optimized placement of data structures in a hierarchy of memory in a computing environment. One or more data structures may be placed in a first scratchpad memory, a second scratchpad memory, an external memory, or a combination thereof in the hierarchy of memory according to a total memory capacity and bandwidth, a level of reuse of the one or more data structures, a number of operations that use each of the one or more data structures, a required duration each the one or more data structures are required to be placed a first scratchpad or a second scratchpad, and characteristics of those of the one or more data structures competing for placement in the hierarchy of memory that are able to co-exist at a same time step. The second scratchpad memory is positioned between the external memory and the first scratchpad memory at one or more intermediary layers.

Optimized hierarchical scratchpads for enhanced artificial intelligence accelerator core utilization

An approach to creating a tamper-resistant field programmable gate array (FPGA) and remotely reprogramming the tamper-resistant FPGA. In one aspect, determining if an encryption key is stored in a physical unclonable function (PUF) of the FPGA. Further, responsive to the encryption key not being stored in a PUF, writing an encryption key in tamper resistant memory associated with a back end of the line (BEOL) of the FPGA. In another aspect, writing a program key and a look-up table (LUT) in the tamper resistant memory.

Trusted field programmable gate array

A method can include obtaining access code data corresponding to an access code transmitted to a user device. The method can further include monitoring the user device. The method can further include determining, based on the monitoring, that the access code is shared. The method can further include initiating, in response to the determining that the access code is shared, an invalidation of the access code.

Authentication security

Three-dimensional (3D) semiconductor memory structures and methods of forming 3D semiconductor memory structures are provided. The 3D semiconductor memory structure includes a chip comprising a memory and Through-Silicon Vias (TSVs). The 3D semiconductor memory structure further includes a hardware accelerator arranged on and coupled face-to-face to the above chip. The 3D semiconductor memory structure also includes a substrate arranged under the under the (3D) semiconductor memory structure and the hardware accelerator and attached to the TSVs and external inputs and outputs of the memory chip and the hardware accelerator.

Heterogeneous integration structure for artificial intelligence computing

Embodiments of the invention are directed to a resistive switching device (RSD). A non-limiting example of the RSD includes a fin-shaped element formed on a substrate, wherein the fin-shaped element includes a source region, a central channel region, and a drain region. A gate is formed over a top surface and sidewalls of the central channel region. The fin-shaped element is doped with impurities that generate interstitial charged particles configured to move interstitially through a lattice structure of the fin-shaped element under the influence of an electric field applied to the RSD.

FinFET resistive switching device having interstitial charged particles for memory and computational applications

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Chappaqua, NY, United States of America

Arvind Kumar