Texas Instruments Corporation

Arvind Jain

Rubin Ajit Parekhji

Sundarrajan Subramanian

Prakash Narayanan

Srinivas Kumar Vooka

Prashant Mohan Kulkarni

Electronic scan circuitry includes a decompressor (), a plurality of scan chains () fed by the decompressor (), a scan circuit () coupled to the plurality of scan chains () to scan them in and out, a masking circuit () fed by the scan chains (), and a scannable masking qualification circuit () coupled to the masking circuit (), the masking qualification circuit () scannable by scan-in of bits by the decompressor () along with scan-in of the scan chains (), and the scannable masking qualification circuit () operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems

Electronic scan circuitry includes a decompressor (), a plurality of scan chains (.i) fed by the decompressor (), a scan circuit () coupled to the plurality of scan chains (.i) to scan them in and out, a masking circuit () fed by the scan chains (.i), and a scannable masking qualification circuit () coupled to the masking circuit (), the masking qualification circuit () scannable by scan-in of bits by the decompressor () along with scan-in of the scan chains (.i), and the scannable masking qualification circuit () operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry

Compressed scan chains with three input mask gates and registers

Decompressed scan chain masking circuit shift register with log2(n/n) cells

Scan chain masking qualification circuit shift register and bit-field decoders

Masking circuit removing unknown bit from cell in scan chain

A scannable integrated circuit () including a functional integrated circuit (P, P) having scan chains, multiple scan decompressors (), each operable to supply scan bits to some of the scan chains (), a shared scan-programmable control circuit (), a tree circuit () coupled with the functional integrated circuit (P, P), the shared scan-programmable control circuit () coupled to control the tree circuit (), and a selective coupling circuit () operable to provide selective coupling with the shared scan-programmable control circuit () for scan programming through any of the multiple scan decompressors (). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.

Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making

Growing community of inventors

Karnataka, India

Arvind Jain