Micron Technology Incorporated

International Business Machines Corporation

Other

Arup Bhattacharyya

Leonard Forbes

Kie Y Ahn

Paul A Farrar

Joseph E Geusic

Alan R Reinberg

Kirk D Prall

Luan C Tran

Robert K Leidy

Durai Vishak Nirmal Ramaswamy

Chung H Lam

Ronald Allen Weimer

Thomas M Graettinger

James K Howard

Robert Michael Geffken

Kyu S Min

Rhett T Brewer

Francis W Wiedman, Iii

Tejas Krishnamohan

Ronald R Silverman

Warren M Farnworth

Hussein Ibrahim Hanafi

Gary Douglas Grise

Pierre B Mollier

Michael L Kerbaugh

Madhukar L Joshi

Wei-Kan Chu

Charles T Kroll

Robert M Quinn

Jeffrey A Robinson

Roy S Bass, Jr

Dominique Basire

Chung Wen Ho

In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.

Memory configurations

In an example, a memory array may include a memory cell around at least a portion of a semiconductor. The memory cell may include a gate, a first dielectric stack to store a charge between a first portion of the gate and the semiconductor, and a second dielectric stack to store a charge between a second portion of the gate and the semiconductor, the second dielectric stack separate from the first dielectric stack.

Memory arrays

The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage element configured to store a first charge transported from the gate element and through the charge transport element, wherein the first charge storage element includes a nitride material, and a second charge storage element configured to store a second charge transported from the gate element and through the charge transport element, wherein the second charge storage element includes a gallium nitride material.

Multifunctional memory cells

The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon oxynitride material, a volatile charge storage element configured to store a first charge transported through the charge transport element, and a non-volatile charge storage element configured to store a second charge transported through the charge transport element, wherein the non-volatile charge storage element includes a gallium nitride material.

The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. A material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.

Trench isolation interfaces

An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.

Memory cells with tunneling materials including lanthanum oxide

In an example, a memory cell may have an interface dielectric adjacent to a semiconductor, a tunnel dielectric adjacent to the interface dielectric, a charge trap adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge trap, and a control gate adjacent to the blocking dielectric.

Memory cell structures

The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.

Integrated computing structures formed on silicon

Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.

Gated diode memory cells

Memory cells programmed via multi-mechanism charge transports are described herein. An example apparatus includes a semiconductor material, a tunneling material formed on the semiconductor material, a charge trapping material formed on the tunneling material, a charge blocking material formed on the charge trapping material, and a metal gate formed on the charge blocking material. The charge trapping material comprises gallium nitride (GaN), and the memory cell is programmed to the target state via the multi-mechanism charge transport such that charges are simultaneously transported to the charge trapping material through a plurality of different channels.

Memory cells programmed via multi-mechanism charge transports

The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. An material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.

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Essex Junction, VT, United States of America

Arup Bhattacharyya