Agere Systems Inc.

Lucent Technologies Inc.

At+t Corp.

Agere Systems Guardian Corp.

At&t Bell Laboratories

Arun Kumar Nanda

Nace Rossi

Sailesh Mansinh Merchant

Pradip Kumar Roy

Ranbir Singh

Sailesh Chittipeddi

Jose Omar Rodriguez

Venkat Raghavan

Alvaro Maury

Laurence D Schultz

Cheryl Anne Bollinger

Ankineedu Velaga

Edward J Vajda

Edward Alan Dein

Mark J Sundahl

Cletus Walter Wilkins, Jr

Frank Miceli

Nace Layadi

Hem M Vaidya

Ajit S Manocha

Virendra V Rana

Charles A Storey

Omar Rodriguez

Cletus Walter Wilkins

Steven Glenn Meester

Fook Loong Chin

A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor

In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

Robust shallow trench isolation structures and a method for forming shallow trench isolation structures

A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

Shallow trench isolation structures and a method for forming shallow trench isolation structures

Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method

The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask over a substrate, etching a trench in the substrate through the hardmask, forming a liner in the trench, depositing an interfacial layer over the liner within the trench and over the hardmask and filling the trench with a dielectric material.

Trench isolation structure and method of manufacture therefor

A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

Control of wafer warpage during backend processing

A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.

Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures

The present invention provides an improved conditioning wheel for conditioning polishing pads used to polish semiconductor wafers. In one embodiment, the conditioning wheel includes a planar body having a metal surface located thereon. The metal surface has abrasive particles embedded therein and a retainer coating deposited over the metal surface and the abrasive particles. The retainer coating inhibits the abrasive particles from dislodging during a conditioning process.

Conditioning wheel for conditioning a semiconductor wafer polishing pad and method of manufacture thereof

The present invention provides a polishing head, for use with a polishing apparatus. In one embodiment, the polishing head includes a carrier head assembly, and a retaining ring having a surface positionable adjacent a polishing pad and couplable to the carrier head assembly and configured to retain a semiconductor wafer therein, the retaining ring having a slurry conduit located therethrough to provide a flow of slurry to the polishing pad.

Polishing head for pressurized delivery of slurry

A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.

Method for reducing dishing related issues during the formation of shallow trench isolation structures

The present invention provides a method for polishing a semiconductor substrate comprising: (a) polishing a metal layer located on a semiconductor wafer with a slurry at a first polishing rate, wherein the slurry has a predetermined concentration of an oxidizing agent therein; (b) forming a diluted slurry by diluting the polishing slurry with a diluent to substantially reduce the predetermined concentration of the oxidizing agent; and (c) polishing the metal layer at a second polishing rate less than the first polishing rate and in the presence of the diluted slurry.

Two phase chemical/mechanical polishing process for tungsten layers

A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

Method for forming shallow trench isolation structures

A method for forming tungsten plugs and layers is disclosed. A thin layer of polysilicon or amorphous silicon is formed within a contact opening. The silicon is exposed to WF,, thereby forming a tungsten plug.

Growing community of inventors

Orlando, FL, United States of America

Arun Kumar Nanda