Taiwan Semiconductor Manufacturing Comp. Ltd.

Arun Achyuthan

Atul Katoch

Sanjeev Kumar Jain

Ruchin Jain

Cormac Michael O'Connell

Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.

Bit line pre-charge circuit for power management modes in multi bank SRAM

A circuit comprises a set of pre-charge and equalization devices, a control signal line, and a word line. The set of pre-charge and equalization devices is configured to pre-charge and equalize a pair of data lines. The control signal line is configured to control the pre-charge and equalization devices. The word line is configured to electrically couple a memory cell to a data line of the pair of data lines. A first voltage value provided to the control signal line is from a first voltage source different from a second voltage source that generates a second voltage value for the word line.

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Arun Achyuthan