Lam Research Corporation

Blue29 Corporation

Kla-tencor Technologies Corporation

Mattson Technology, Inc

Artur Kolics

Igor C Ivanov

Praveen Nalla

Nanhai Li

Fritz C Redeker

George Andrew Antonelli

Jonathan Xiaohang Zhang

William T Lee

Novy Sastrawati Tjokro

Adrien Lavoie

Dennis Michael Hausmann

Jeffrey S Marks

Bhadri N Varadarajan

Patrick A Van Cleemput

Richard Alan Gottscho

Kaihan Abidi Ashtiani

Sirish K Reddy

Yaxin Wang

Larry Zhao

Derek Wong

Thomas Joseph Knisley

Nicolai Petrov

Marina Polyanskaya

Yezdi N Dordi

Shijian Li

William Thie

Chiu H Ting

Tiruchirapalli Arunagiri

Weiguo Zhang

Xiaomin Bin

Lie Zhao

Samantha SiamHwa Tan

Seshasayee Varadarajan

Ron Rulkens

Taeseung Kim

Patrick Little

Sergey D Lopatin

Bart Jan Van Schravendijk

Deenesh Padhi

Jengyi Yu

Keren Jacobs Kanarik

Jason Stephen Corneille

Robert W Fiordalice

Nerissa Sue Draeger

Faivel S Pintchovski

Robert D Tas

Boris Volosskiy

Dries Dictus

Darin Birtwhistle

Chee Yung Chan

Mark Weise

Wen Zhong Kong

Shashank Ravindra Kulkarni

Nancy E Gilbert

Aman Jain

Nalla Praveen

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

Vacuum-integrated hardmask processes and apparatus

A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a trench and an opening formed to extend from a bottom of the trench to an underlying conductive material, with the underlying conductive material exposed at a bottom of the opening. The dual damascene structure is exposed to a sealing process by which the exposed surfaces of the dielectric material in the opening are sealed without covering the underlying conductive material exposed at the bottom of the opening. The sealing process can be one or more of deposition of a flowable film, deposition of an amorphous carbon barrier layer, and formation of a self-assembled monolayer of an amino group. After the sealing process, an electroless deposition process is performed to fill the opening with a metallic material in a bottom-to-top manner up to the bottom of the trench.

Interlevel conductor pre-fill utilizing selective barrier deposition

A method of depositing a metal seed for performing bottom-up gapfill of features of a substrate includes providing a substrate including a plurality of features; flowing a dilute metal precursor solution into the features, wherein the dilute metal precursor solution includes a metal precursor and a dilution liquid; evaporating the dilution liquid to locate the metal precursor at bottoms of the plurality of features; exposing the substrate to a plasma treatment to reduce the metal precursor to at least one of a metal or a metal alloy and to form a seed layer; performing a heat treatment on the substrate; and using a selective gapfill process to fill the features with a transition metal in contact with the seed layer.

Methods for wet metal seed deposition for bottom up gapfill of features

A substrate having at least one device; wherein the substrate having a conductive layer disposed on a top surface of the substrate, the top surface having an edge exclusion region defined as an annular area that extends to an edge of the substrate, the top surface of the substrate further having a process region defined as a central area of the substrate that extends to about the annular area; wherein the substrate having a metallic material deposited over the conductive layer at the edge exclusion region, wherein a thickness of the metallic material reduces electrical resistance of the metallic material at the edge exclusion region; wherein the thickness of the metallic material and resulting reduced electrical resistance for an applied electrical current to the metallic material facilitates increasing a rate at which the process region is plated as a result of the applied electrical current and an applied electroplating solution.

Metallization of the wafer edge for optimized electroplating performance on resistive substrates

Implementations of the methods and apparatus disclosed herein relate to pore sealing of porous dielectric films using flowable dielectric material. The methods involve exposing a substrate having an exposed porous dielectric film thereon to a vapor phase dielectric precursor under conditions such that a flowable dielectric material selectively deposits in the pores of the porous dielectric material. The pores can be filled with the deposited flowable dielectric material without depositing a continuous film on any exposed metal surface.

Method for selectively sealing ultra low-k porous dielectric layer using flowable dielectric film formed from vapor phase dielectric precursor

Atomic layer etching (ALE) enables effective filling of small feature structures on semiconductor and other substrates, such as contacts and vias, by bottom-up fill, for example electroless deposition (ELD) of cobalt.

Atomic layer etching for enhanced bottom-up feature fill

A solution for providing electroless deposition of a metal layer on a substrate is provided. A solvent is provided. A metal precursor is provided to the solvent. A first borane containing reducing agent is provided to the solvent. A second borane containing reducing agent is provided to the solvent, wherein the first borane containing reducing agent has a deposition rate of at least five times a deposition rate of the second borane containing reducing agent, and wherein the solution is free of nonborane reducing agents.

Method of electroless plating using a solution with at least two borane containing reducing agents

A method for filling vias formed in a dielectric layer with a metal or metal alloy that has a low solubility with copper over copper containing interconnects, wherein the vias are part of a dual damascene structure with trenches and vias is provided. A sealing layer of a first metal or metal alloy that has a low solubility with copper is selectively deposited directly on the copper containing interconnects in at bottoms of the vias, wherein sidewalls of the dielectric layer forming the vias are exposed to the depositing the sealing layer, and wherein the first metal or metal alloy that has a low solubility is selectively deposited to only form a layer on the copper containing interconnects. A via fill of a second metal or metal alloy that has a low solubility with copper is electrolessly deposited over the sealing layer, which fills the vias.

Dual damascene fill

A system for electroless deposition on a substrate is provided, including the following: a chamber; a substrate support configured to receive a substrate having a conductive layer disposed on a top surface of the substrate, the top surface of the substrate having an edge exclusion region and a process region, wherein the substrate support is configured to rotate the substrate; a solution container configured to hold an electroless deposition solution; a dispenser configured to provide a flow of the electroless deposition solution; a controller, the controller configured to direct the flow of the electroless deposition solution toward the edge exclusion region while the substrate is rotated, the flow being directed away from the process region, the electroless deposition solution plates metallic material over the conductive layer at the edge exclusion region, to produce an increased thickness of the metallic material that reduces electrical resistance.

A pre-fill solution for application onto a substrate surface prior to a fill operation is provided, the fill operation defined by application of an electroless deposition solution onto the substrate surface to deposit a metallic material in an etched feature, the substrate surface having metallic contaminants generated from an etch operation that generated the etched feature in the substrate surface, the pre-fill solution effective for preventing the electroless deposition solution from depositing on the metallic contaminants, the pre-fill solution comprising: a surfactant, the surfactant configured to enhance wetting of the substrate surface, the concentration of the surfactant in the solution being approximately in the range of 10 ppm to 2000 ppm, wherein the surfactant is an amphoteric surfactant; oxalic acid dihydrate; and hypophosphorous acid as a pH adjusting agent configured to reduce the pH of the solution to approximately less than 2 during the application onto the substrate surface.

Pre-fill wafer cleaning formulation

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Dublin, CA, United States of America

Artur Kolics