Hyundai Electronics America, Inc.

Winbond Electronics Corporation

Other

Arthur Wang

Jein-Chen Young

Ming Sang Kwan

Kenlin Huang

Harry Luan

Kai-Cheng Chou

Ming-Sang Kwan

Kai Cheng Chou

Harry Laun

J C Young

Kaicheng Chou

An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e.g., PrCaMnO). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.

Stackable resistive cross-point memory with schottky diode isolation

A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl+HBr+CF) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Method and resulting structure for PCMO film to obtain etching rate and mask to selectively by inductively coupled plasma

An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface. A word line is overlying the planarized surface. The word line is coupled to the first word gate and the second word gate and is overlying the HDP plasma dielectric. The device has a refractory metal layer formed overlying the word line, a hard mask layer overlying the refractory metal layer, and a cap layer formed overlying the hard mask layer. The word line, refractory metal layer, hard mask layer, and cap layer form a planarized structure.

Method and structure for fabricating non volatile memory arrays

A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about &minus;9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.

Erase method for flash memory

A method of programming an electrically programmable memory cell which cell includes a transistor formed in a semiconductor substrate of first conductivity type having a surface a first well region of second conductivity type is disposed in the substrate adjacent the surface thereof. A second well region of first conductivity type is disposed in the first well region adjacent the surface. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes raising the control gate to a first selected potential no greater than 9.0 volts, raising the drain to a potential to no more than 5.0 volts, coupling the source region to ground potential, coupling the first well region of second conductivity type to ground potential, and placing the second well region at a potential below ground potential.

Method of operating flash memory

A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential no more negative than 6.5 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential no more positive than 8.0 volts.

A semiconductor structure for a flash memory has memory cells which are formed in a first conductivity type well, which in turn is formed within an opposite conductivity type well. The opposite conductivity type well is formed in the substrate. Additional regions within each of the first and opposite conductivity type wells are used to provide electrical connections to the corresponding well. This structure is particularly advantageous because it provides the ability to operate the flash memory with considerably lower operating potentials than prior art flash memories.

Semiconductor structure for flash memory enabling low operating potentials

Display frame

A container for pencils and the like is convertible into a holder for those pencils by reversely folding an outer cover of the container at a position intermediate with lengths to provide two compartments in parallelism with each other, and which are usable as a pencil holder.

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San Jose, CA, United States of America

Arthur Wang