Motorola Corporation

Arthur D Kahlich

Kenneth W Jones

Mark D Bader

A multiple-way, set associative cache memory (20) allows burst read and burst write operations to occur simultaneously on different columns within a memory block during a read-modify-write operation. This is accomplished by using a write column logic (47) and a read column logic (51) to delay write column decode signals by one clock cycle from the read column decode signals. When data is being burst into and out of the cache during the read-modify-write operation, the first read cycle from the cache array (40) occurs, and one clock cycle later, the first write cycle occurs. The first write cycle occurs during the same time interval as the second read cycle. This increases the speed of a read-modify-write operation, relaxes timing constraints on the read and write operations, while reducing the power consumption of the cache.

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Austin, TX, United States of America

Arthur D Kahlich