Intel Corporation

Intel Corporatiion

Arnab Sen Gupta

Matthew V Metz

Van H Le

Abhishek A Sharma

Jack T Kavalieros

Tahir Ghani

Nazila Haratipour

Gilbert W Dewey

Seung Hoon Sung

Kaan Oguz

Justin R Weber

Shriram Shivaraman

I-Cheng Tung

Benjamin Chu-Kung

Charles C Kuo

Brian S Doyle

Uygar E Avci

Noriyuki Sato

Prashant Majhi

Bernhard Sell

Hui Jae Yoo

Christopher J Jezewski

Chia-Ching Lin

Travis W LaJoie

Pei-Hua Wang

Chieh-Jen Ku

Urusa Alaan

Sou-Chi Chang

Sarah Atanasov

Anand S Murthy

Ian A Young

Elijah V Karpov

Siddharth Chouksey

Glenn A Glass

Paul B Fischer

Sean T Ma

Harold W Kennel

Kimin Jun

Ashish Verma Penumatcha

Ibrahim Ban

Elliot Tan

Miriam Ruth Reshotko

Lawrence D Wong

Ayan Kar

Ryan Keech

Kevin P O'brien

Sudarat Lee

Nicholas A Thomson

Edris M Mohammed

Abhishek Sharma

Koustav Ganguly

Jitendra Kumar Jha

Ryan E Arch

Mengcheng Lu

Benjamin Orr

Yu-Jin Chen

Ande Kitamura

Ved V Gund

Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.

Capacitor with dual dielectric layers

Embodiments described herein may be related to apparatuses, processes, and techniques related MIM capacitors that have a multiple trench structure to increase a charge density, where a dielectric of the MIM capacitor includes a perovskite-based material. In embodiments, a first electrically conductive layer may be coupled with a top metal layer of the MIM, and/or a second conductive layer may be coupled with a bottom metal layer of the MIM to reduce RC effects. Other embodiments may be described and/or claimed.

Capacitor with an electrically conductive layer coupled with a metal layer of the capacitor

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

Compositional engineering of Schottky diode

In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The RF resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

Digitally controlled lithographically-defined multi-frequency acoustic resonators

A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.

Passivation layers for thin film transistors

Transistor structures may include a metal oxide contact buffer between a portion of a channel material and source or drain contact metallization. The contact buffer may improve control of transistor channel length by limiting reaction between contact metallization and the channel material. The channel material may be of a first composition and the contact buffer may be of a second composition.

Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

ESD protection decoupled from diffusion

Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures

Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

Capacitors with built-in electric fields

An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

Thin film transistors having a backside channel contact for high density memory

Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

Low resistance approaches for fabricating contacts and the resulting structures

Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

Monolithic memory stack

Passivation layers for thin film transistors and methods of fabrication

A vertical transistor structure includes a material stack having a source material, a drain material, and a channel material therebetween. The vertical transistor structure further includes a gate electrode adjacent to a sidewall of the stack, where the sidewall includes the channel material, and at least a partial thickness of both the source material and the drain material. A gate dielectric is present between the sidewall of the stack and the gate electrode. The vertical transistor structure further includes a first metallization over a first area of the stack above the gate dielectric layer, and in contact with the gate electrode on sidewall of the stack. A second metallization is adjacent to the first metallization, where the second metallization is over a second area of the stack, and in contact with the source material or the drain material.

Vertical transistors for ultra-dense logic and memory applications

Growing community of inventors

Hillsboro, OR, United States of America

Arnab Sen Gupta