Infineon Technologies Ag

International Business Machines Corporation

Infineon Technologies North America Corp.

Armin Fischer

Alexander Von Glasow

Fen Chen

Philipp Riess

Franz Ungar

Jochen Von Hagen

Markus Schwerd

Johann Helneder

Wolfgang Walter

Heinrich Körner

Sabine Penka

A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip.

Integrated circuit with pads connected by an under-bump metallization and method for production thereof

A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.

Method for detecting stress migration properties

Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.

MIM capacitors in semiconductor components

A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.

Method of forming metal ion transistor

Integrated circuit with additional mini-pads connected by an under-bump metallization and method for production thereof

Device for detecting stress migration properties

A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.

Metal ion transistor

A set of integrated capacitor arrangements is presented, each of which has a circuitry-effective main capacitor and a connectable correction capacitor. Each capacitor arrangement has an electrically conductive antifuse connection and antifuse interruption between the correction capacitor and the main capacitor, which are produced after the main capacitor has been formed. The connection and interruption enable the capacitance of the capacitor arrangement to be corrected.

Set of integrated capacitor arrangements, especially integrated grid capacitors

A method for producing a semiconductor product. Semiconductor product components are formed in a semiconductor product region of the substrate. A layer made of low-k material is subsequently formed on the substrate. Electrically conductive interconnects are formed in and/or on the layer made of low-k material. The layer of low-k material is provided in a wiring plane of the semiconductor product region for the electrical insulation of the interconnects from one another. A grid cap region of the substrate is subjected to a spacially delimited treatment such that the value of the dielectric constant is increased in the crossover region. Accordingly, an interconnect to interconnect capacitance is formed as grid cap capacitance from the interconnects arranged in the crossover region and the material and increased value of dielectric constant. Further, the dielectric constant of the low-k material remains unchanged in the semiconductor product region.

Method for producing a grid cap with a locally increased dielectric constant

An integrated test circuit arrangement is provided that contains integrated test structures, at least one integrated heating element, an integrated detection unit, an integrated supply unit, and a control unit. The integrated detection unit detects at least one physical property for each of the test structures. The integrated supply unit supplies each of the test structures with a current or a voltage in switchable fashion independently of one another. The control unit is connected to outputs of the detection unit on an input side and controls the supply unit dependent on the detection results.

Integrated test circuit arrangement and test method

An integrated circuit arrangement having a metallization layer, an interconnect dielectric, electrically conductive interconnect intermediate material, electrically conductive connecting sections, connecting section dielectric between the connecting sections, and connecting section intermediate material. The metallization layer contains electrically conductive interconnects between which the interconnect dielectric is disposed. The electrically conductive interconnect intermediate material is arranged between a side area of an interconnect and the interconnect dielectric. The electrically conductive connecting sections in each case form a section of an electrically conductive connection to or from an interconnect and the connecting section dielectric is between the connecting sections. The connecting section intermediate material is arranged in each case between a connecting section and the connecting section dielectric and/or between a connecting section and an interconnect. The interconnect intermediate material and the connecting section intermediate material make contact with one another at at least one connection.

Integrated circuit arrangement with intermediate materials and associated components

An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.

Growing community of inventors

Munich, Germany

Armin Fischer