Maxim Integrated Products, Inc.

Applied Materials, Inc.

Other

Qualcomm Incorporated

Qualcomm Technologies, Inc.

Arkadii V Samoilov

Yihwan Kim

Nicole Dorene Kerness

Joy T Jones

Ali Zojaji

Zhihai Wang

Viren V Khandekar

Yi-Sheng Anthony Sun

Yong L Xu

Nicholas C Dalida

Tyler Parent

Peter R Harper

Reynante Tamunan Alvarado

Zhiyuan Ye

Pirooz Parvarandeh

Lance A Scudder

Arvin Emadi

Lori D Washington

Xuejun Ying

Chiung C Lo

Xiaowei Li

Jinsong Tang

Xiao Chen

Paul B Comita

Errol C Sanchez

Tiao Zhou

Tie Wang

David K Carlson

Dan Maydan

Stephen Charles Gerber

Richard Stacy Withers

Ronald Bonshaw Koo

Christopher Francis Edwards

Dale R Dubois

Larry Yu Wang

Jean Rene Vatus

David Johnson

Herman Diniz

Duane Wilcoxen

Shahab Khandan

Peter McNally

Rey Alvarado

Christopher T Fulmer

Albert M Bergemont

Roger N Anderson

Jerome Chandra Bhat

Prashanth S Holenarsipur

Sriram Muthukumar

Kumar Nagarajan

David Masayuki Ishikawa

Craig Metzner

Anand K Chamakura

Ke-Cai Zeng

Cheng-Wei Pei

Martin T Mason

Phillip J Benzel

Amit Subhash Kelkar

Khanh Tran

Karthik Thambidurai

John Philip Hanks

Richard I Olsen

Craig A Easson

Bradley Mitchell Curelop

Vijay Ullal

Xiansong Chen

Abhishek Sahasrabudhe

David R Carlson

Kaysar M Rahim

Chiung-C Lo

James Patrick Long

S Kaysar Rahim

Rohini Kodali

Dean E Berlin

Annie A Karpati

An optical sensor package includes a substrate, a wall disposed upon the substrate, and a cover layer disposed on the wall. The substrate, the wall, and the cover layer at least partially define a cavity. The optical sensor package also includes a sensor disposed upon the substrate within the cavity. A cloaking layer is disposed upon to the cover layer. The cloaking layer is transmissive to at least a portion of a light spectrum and is configured to at least partially conceal the sensor. In some examples, the optical sensor package also includes a light source disposed upon the substrate within another cavity at least partially defined by the wall and the cover layer.

Optical sensor packages employing cloaking layers

A device and techniques for fabricating the device are described for forming a wafer-level thermal sensor package using microelectromechanical system (MEMS) processes. In one or more implementations, a wafer level thermal sensor package includes a thermopile stack, which includes a substrate, a dielectric membrane, a first thermoelectric layer, a first interlayer dielectric, a second thermoelectric layer, a second interlayer dielectric, a metal connection assembly, a passivation layer, where the passivation layer includes at least one of a trench or a hole, and where the substrate includes a cavity adjacent to the at least one trench or hole, and a bond pad disposed on the passivation layer and electrically coupled to the metal connection assembly; and a cap wafer assembly coupled to the thermopile stack, the cap wafer assembly including a wafer having a cavity formed on a side of the wafer configured to be adjacent to the thermopile stack.

MEMS-based wafer level packaging for thermo-electric IR detectors

A fingerprint sensor is described that includes a thin protective cover layer on a sensor glass layer with receive circuitry between the thin protective cover layer and the sensor glass layer. In an implementation, a fingerprint sensor assembly includes a controller; a metal layer configured to be electrically coupled to the controller; a transmit layer electrically connected to the metal layer and the controller; a sensor glass layer, where the transmit layer is disposed on a first side of the sensor glass layer, and where the transmit layer is electrically coupled to the controller; a receive layer disposed on a second side of the sensor glass layer, where the receive layer is electrically coupled to the controller; and a protective cover layer disposed on the receive layer.

High-resolution electric field sensor in cover glass

A gas concentration sensor is includes an integrated die-form electromagnetic radiation source and an integrated die-form infrared detector. In one or more implementations, the gas concentration sensor includes a package substrate defining at least one aperture, a gas permeable mesh coupled to the package substrate and covering at least a portion of the at least one aperture, a die-form electromagnetic radiation source positioned in an interior region of the package substrate, a die-form detector positioned in the interior region of the package substrate, and control circuitry operably coupled to the die-form detector and configured to detect and calibrate one or more signal outputs from the die-form detector to determine a gas concentration within the interior region of the package substrate. The gas concentration sensor can be configured for specific detection of various gases through control of the spectral wavelengths emitted by the electromagnetic radiation source(s) and/or detected by the detector(s).

Fully integrated gas concentration sensor

Techniques are provided to furnish a light sensor that includes a filter positioned over a photodetector to filter visible and infrared wavelengths to permit the sensing of ultraviolet (UV) wavelengths. In one or more implementations, the light sensor comprises a semiconductor device (e.g., a die) that includes a substrate. A photodetector (e.g., photodiode, phototransistor, etc.) is formed in the substrate proximate to the surface of the substrate. In one or more implementations, the substrate comprises a silicon on insulator substrate (SOI). A filter (e.g., absorption filter, interference filter, flat pass filter, McKinlay-Diffey Erythema Action Spectrum-based filter, UVA/UVB filter, and so forth) is disposed over the photodetector. The filter is configured to filter infrared light and visible light from light received by the light sensor to at least substantially block infrared light and visible light from reaching the photodetector. The thickness of the SOI substrate can be tailored to modify received UV/visible wavelength ratios.

Ultraviolet sensor having filter

Wafer-level package semiconductor devices are described that have a smallest distance between two adjacent attachment bumps smaller than about twenty-five percent (25%) of a pitch between the two adjacent attachment bumps. The smallest distance between the two adjacent attachment bumps allows for an increase in the number of attachment bumps per area without reducing the size of the bumps, which increases solder reliability. The increased solder reliability may reduce stress to the attachment bumps, particularly stress caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on.

Wafer-level package device

A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.

Enhanced board level reliability for wafer level packages

A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.

Wafer level device and method with cantilever pillar structure

Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate.

Fan-out and heterogeneous packaging of electronic components

Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Semiconductor device having a die and through-substrate via

A wafer level package includes a wafer, a lead disposed of the wafer for connecting the wafer to an electrical circuit, and a core disposed of the lead. In some embodiments, the lead disposed of the wafer is a copper pillar, and the core is plated onto the copper pillar. In some embodiments, the core is polymer screen-plated onto the lead. In some embodiments, the core extends between at least approximately thirty-five micrometers (35 &#x3bc;m) and fifty micrometers (50 &#x3bc;m) from the lead. In some embodiments, the core covers between at least approximately one-third (&#x2153;) and one-half (&#xbd;) of the surface area of the lead. In some embodiments, the core comprises a stud-shape extending from the lead. In some embodiments, the core extends perpendicularly across the lead. In some embodiments, the core extends longitudinally along the lead. Further, a portion of the core can extend perpendicularly from a longitudinal core.

Solder fatigue arrest for wafer level package

A fingerprint sensor is described that includes a thin protective cover layer on a sensor glass layer with receive circuitry between the thin protective cover layer and the sensor glass layer. In an implementation, a fingerprint sensor assembly includes a controller; a metal layer configured to be electrically coupled to the controller; a transmit layer electrically connected to the metal layer and the controller; a sensor glass layer including at least one through-glass via, where the transmit layer is disposed on a first side of the sensor glass layer, and where the transmit layer is electrically coupled to the at least one through-glass via; a receive layer disposed on a second side of the sensor glass layer, where the receive layer is electrically coupled to the at least one through-glass via; and a protective cover layer disposed on the receive layer.

Techniques are described to furnish an IR suppression filter, or any other interference based filter, that is formed on a transparent substrate to a light sensor. In one or more implementations, a light sensor includes a substrate having a surface. One or more photodetectors are formed in the substrate. The photodetectors are configured to detect light and provide a signal in response thereto. An IR suppression filter configured to block infrared light from reaching the surface is formed on a transparent substrate. The light sensor may also include a plurality of color pass filters disposed over the surface. The color pass filters are configured to filter visible light to pass light in a limited spectrum of wavelengths to the one or more photodetectors. A buffer layer is disposed over the surface and configured to encapsulate the plurality of color pass filters and adhesion layer.

Light sensor having a contiguous IR suppression filter and transparent substrate

Techniques are described to furnish an IR suppression filter that is formed on a glass substrate to a light sensor. In one or more implementations, a light sensor includes a substrate having a surface. One or more photodetectors are formed in the substrate and configured to detect light and provide a signal in response thereto. An IR suppression filter configured to block infrared light from reaching the surface is formed on a glass substrate. The light sensor also includes a plurality of color pass filters disposed over the surface. The color pass filters are configured to filter visible light to pass light in a limited spectrum of wavelengths to the one or more photodetectors. A buffer layer is disposed over the surface and configured to encapsulate the plurality of color pass filters and adhesion layer. The light sensor further includes through-silicon vias to provide electrical interconnections between different conductive layers.

Light sensor having transparent substrate and through-substrate vias and a contiguous IR suppression filter

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Saratoga, CA, United States of America

Arkadii V Samoilov