Newport Fab, LLC

Conexant Systems, Inc.

Arjun Kar-Roy

David J Howard

Marco Racanelli

Michael J DeBar

Jeff Rose

Paul D Hurwitz

Todd Thibeault

Paul Kempf

Volker Blaschke

Jinshu Zhang

Chris Cureton

Amol M Kalburge

Kevin Q Yin

Dieter Dornisch

Phil N Sherman

A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

Self-supported MEMS structure and method for its formation are disclosed. An exemplary method includes forming a polymer layer over a MEMS plate over a substrate, forming a trench over the MEMS plate, forming an oxide liner in the trench on sidewalls of the trench, forming a metal liner over the oxide liner in the trench, and depositing a metallic filler in the trench to form a via. The method further includes removing the polymer layer such that the via and the MEMS plate form the self-supported MEMS structure, where the oxide liner provides mechanical rigidity for the metallic filler of the via. An exemplary structure formed by the disclosed method is also disclosed.

Scalable self-supported MEMS structure and related method

A light sensor having a chemically resistant and robust reflector stack is disclosed. The reflector stack is formed over a substrate, and includes an adhesion layer, a patterned reflector layer over the adhesion layer, and a smoothing layer over the patterned reflector layer. The patterned reflector layer has a substantially flat top surface. A conformal passivation layer covers the reflector stack. An absorbing layer is situated above the reflector stack and separated from the reflector stack. The absorbing layer is supported by vias over the substrate. The absorbing layer is connected to at least one resistor, where a resistance of the at least one resistor varies in response to light absorbed by the absorbing layer. The vias are disposed on via landing pads on the substrate.

Light sensor with chemically resistant and robust reflector stack

Self-supported MEMS structure and method for its formation are disclosed. An exemplary method includes forming a polymer layer over a MEMS plate over a substrate, forming a via collar along sidewalls of a first portion of a trench over the polymer layer, and forming a second portion of the trench within the polymer layer. The method also includes forming an oxide liner in the trench lining sidewalls of the via collar and sidewalls of the second portion of the trench, depositing a metallic filler in the trench to form a via, and forming a metal cap layer over the via collar and the metallic filler. The method further includes removing a portion of the metal cap layer to form a via cap, and removing the polymer layer such that the via is supported only on a bottom thereof by the substrate. An exemplary structure formed by the disclosed method is also disclosed.

Robust MEMS structure with via cap and related method

A disclosed method for fabricating a structure in a semiconductor die comprises steps of implanting a deep N well in a substrate, depositing an epitaxial layer over the substrate, and forming a P well and a lateral isolation N well over the deep N well, wherein the lateral isolation N well and the P well are fabricated in the substrate and the epitaxial layer, and wherein the lateral isolation N well laterally surrounds the P well, and wherein the deep N well and the lateral isolation N well electrically isolate the P well. Implanting a deep N well can comprise steps of depositing a screen oxide layer over the substrate, forming a mask over the screen oxide layer, implanting the deep N well in the substrate, removing the mask, and removing the screen oxide layer. Depositing the epitaxial layer can comprise depositing a single crystal silicon over the substrate.

Deep N wells in triple well structures

According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.

Method for forming deep silicon via for grounding of circuits and devices, emitter ballasting and isolation

Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation

According to an exemplary embodiment, a method for fabricating a backside through-wafer via in a processed wafer includes forming a through-wafer via opening through a substrate and extending the through-wafer via opening through at least one interlayer dielectric layer situated over the substrate. The method further includes forming a metal layer in the through-wafer via opening, where the metal layer forms an electrical connection to substrate. The metal layer is also in electrical contact with an interconnect metal segment situated above the at least one interlayer dielectric layer. The method further includes performing a thinning process to reduce the substrate to a target thickness before forming the through-wafer via opening. The method further includes forming an electrically conductive passivation layer on the metal layer and over a bottom surface of the substrate, where the electrically conductive passivation layer is in electrical contact with the metal layer and the substrate.

Method for fabricating a backside through-wafer via in a processed wafer and related structure

According to an exemplary embodiment, a liquid crystal on silicon (LCoS) structure includes a number of pixel electrodes overlying an interlayer dielectric, where diagonally adjacent pixel electrodes are separated by a gap. The LCoS structure further includes a self-planarizing passivation dielectric situated over the pixel electrodes and in the gap, where the self-planarizing passivation dielectric has a selected thickness. The self-planarizing passivation dielectric can be an Oxide-Nitride-Oxide (ONO) stack. The selected thickness of the self-planarizing passivation dielectric causes the self-planarizing passivation dielectric to have a substantially planar top surface. In one embodiment, the thickness of the self-planarizing passivation dielectric can be approximately equal to twice a width of the gap.

Self-planarized passivation dielectric for liquid crystal on silicon structure and related method

According to an exemplary embodiment, a method for fabricating a top conductive layer in a semiconductor die includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the semiconductor die. The method further includes extending the through-wafer via opening through a substrate of the semiconductor die to reach a target depth. The method further includes forming a through-wafer via conductive layer in the through-wafer via opening, and concurrently forming the top conductive layer over an exposed top metal segment.

Fabricating a top conductive layer in a semiconductor die

According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench.

Deep trench isolation and method for forming same

According to an exemplary embodiment, a method for fabricating a frontside through-wafer via in a processed wafer includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the processed wafer. The method further includes extending the through-wafer via opening through a substrate to a target depth. The method further includes forming a first conductive layer in the through-wafer via opening and over a through-wafer via pad, which is situated over the at least one interlayer dielectric layer. The first conductive layer in the through-wafer via opening forms an electrical connection between the substrate and the through-wafer via pad. The method further includes forming a second conductive layer on the backside surface of the processed wafer, where the second conductive layer is in electrical contact with the first conductive layer and the substrate.

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Irvine, CA, United States of America

Arjun Kar-Roy