Texas Instruments Corporation

Texas Instruments Incorpated

Antonio L P Rotondaro

Mark R Visokay

Luigi Colombo

James Joseph Chambers

Douglas E Mercer

Rajesh B Khamankar

Malcolm John Bevan

Haowen Bu

Robert Kraft

Patricia Beauregard Smith

Deborah J Riley

Trace Quentin Hurd

Hiroaki Niimi

Seetharaman Sridhar

Manoj Mehrotra

Donald L Plumton

Mona M Eissa

Duane E Carter

Sunil V Hattangady

Reima Tapani Laaksonen

Yuanning Chen

Puneet Kohli

Manuel A Quevedo-Lopez

David Brian Aldrich

Katherine E Violette

Karen Kirmse

Stephen W Russell

Rebecca J Gale

Eric C Williams

Charlotte M Appel

A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Gate structure and method

There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900&#xb0; C. or greater.

Semiconductor device manufactured using a laminated stress layer

CMOS gate dielectric made of high-k metal silicates by reaction of metal with silicon dioxide at the silicon surface. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Gate dielectric and method

A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

Method and system for forming dual work function gate electrodes in a semiconductor device

CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Integrated circuits with composite gate dielectric

The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer () over a gate dielectric layer () located on a substrate (), and patterning the gate electrode layer () using a combination of a dry etch process () and a wet etch process ().

Multi-step process for patterning a metal gate electrode

A method for improving high-&#x3ba; gate dielectric film () properties. The high-&#x3ba; film () is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient () with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient () with a low partial pressure of reducer to remove defects and impurities.

Method for controlling defects in gate dielectrics

A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

A dielectric layer () is formed over a semiconductor () that contains a first region () and a second region (). A polysilicon layer is formed over the dielectric layer () and over the first region () and the second region (). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions () and () respectively. If desired a cladding layer () can be formed above the metal gate structures.

Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound

The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to channel regions of devices while mitigating masking operations employed. A CAPOLY layer is formed over an NMOS region of a semiconductor device (). A recess etch is performed on active regions of devices within a PMOS region of the semiconductor device () and the CAPOLY layer prevents etching of devices within an NMOS region of the semiconductor device. Subsequently, an epitaxial formation process () is performed that forms or deposits epitaxial regions and introduces a first type of strain across the channel regions in the PMOS region. Then, the semiconductor device is annealed () to cause the CAPOLY layer to introduce a second type of strain across the channel regions in the NMOS region. After annealing, the CAPOLY layer is removed ().

Method to selectively recess ETCH regions on a wafer surface using capoly as a mask

Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.

Method for fabricating transistor gate structures and gate dielectrics thereof

CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.

Growing community of inventors

Dallas, TX, United States of America

Antonio L P Rotondaro