Stmicroelectronics Gmbh

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Stmicroelectronics S.r.l.

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Antonio Imbruglia

Raffaele Zambrano

Charles D Waggoner

Tsiu Chiu Chan

Richard Ferrant

Maria Leena Airaksinen

Sebastiano Moscuzza

Giovanni Benenati

A radiation hardened memory device includes active gate isolation structures placed in series with conventional oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage potential resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Radiation hardened semiconductor memory with active isolation regions

An electronic device for controlling oscillation of an output voltage about a final value includes a semiconductor substrate, and at least one output stage on the semiconductor substrate. The at least one output stage includes at least one output transistor for providing an output voltage to an external load connected thereto. The output transistor includes a plurality of transistor legs connected in parallel and having different channel lengths. Each transistor leg is individually turned on and at different times for controlling oscillation of the output voltage about the final value.

Electronic device for controlling the &ldquo;bouncing&rdquo; in electronic circuits integrated on semiconductor substrate

An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit. The conductor includes at least one fold for extending the length of the conductor to exceed the distance between the input bonding pad and the receiver input node.

Integrated circuit with improved electrostatic discharge protection circuitry

Integrated circuit with improved electrostatic discharge protection

A CMOS logic circuit with biased inputs to a predetermined logic level, being of a type including at least one signal input terminal and logic gates for acting on an input signal, and further including a circuit portion which is connected to the signal input terminal, and includes a high-value resistance effective to bias the input signal.

CMOS pull-up input network

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Catania, Italy

Antonio Imbruglia