Mcgill University

Dft Microsystems, Inc.

Antonio H Chan

Gordon W Roberts

Mohamed M Hafed

Clarence K L Tam

Sébastien Laberge

Bardia Pishdad

Geoffrey D Duerden

A module (') containing an integrated testing system () that includes one or more measurement engines () tightly coupled with a compute engine (). The one or more measurement engines include at least one stimulus instrument () for exciting circuitry of a device-under-test () with one or more stimulus signals, and at least one measurement instrument () that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry () for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine () providing two-way communications between the integrated testing system automated testing equipment () and/or a dedicated user interface () residing on a host computer ().

System and method for testing integrated circuits

In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.

Timing measurement device using a component-invariant vernier delay line

Growing community of inventors

Brossard, Canada

Antonio H Chan