Micron Technology Incorporated

Anton P Eppich

Fei Wang

The present disclosure includes apparatuses and methods for vertical access line in a folded digitline sense amplifier. An example apparatus includes an array of memory cells. The memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region. A pair of adjacent memory cells can share a digitline contact at the second source/drain region. A storage node contact can be coupled to respective first source/drain regions and each gate can be connected to vertically oriented access lines formed on opposing side of a depletion region to each access device. An insulator material can be patterned between adjacent digitlines to isolate adjacent memory cells.

Vertical access line in a folded digitline sense amplifier

Some embodiments include an integrated assembly having a set of true digit-lines and a set of complementary digit-lines. Each of the complementary digit-lines is comparatively coupled with an associated one of the true digit-lines. A semiconductor substrate is under the true digit-lines. The semiconductor substrate includes semiconductor features which project upwardly from a semiconductor base and which extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source/drain regions are within the semiconductor features and second source/drain regions are within the semiconductor base. The true digit-lines are coupled with the first source/drain regions. Wordlines are along the opposing sidewalls and include gating regions which gatedly couple the first source/drain regions with the second source/drain regions. Storage-elements are coupled with the second source/drain regions. In some embodiments, memory may utilize a 4Flayout.

Integrated assemblies

Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask includes an optically transmissive substrate having a sub-resolution assist device that further includes a first optical attenuation region and a spaced-apart second optical attenuation region, and an optically transmissive phase adjustment region interposed between the first optical attenuation region and the second optical attenuation region, the phase adjustment region being configured to change a phase of incident illumination radiation by altering an optical property of the substrate.

Sub-resolution assist devices and methods

The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6Fis disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

DRAM cell design with folded digitline sense amplifier

According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at least a portion of a first word line located between a first drain and the source, and at least a portion of a second word line located between a second drain and the source, which word lines define a second axis. The memory device further comprises a digit line coupled to the source, wherein the digit line forms a substantially zig-zag pattern.

Relaxed-pitch method of aligning active area to digit line

A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Memory cell with a vertically oriented transistor coupled to a digit line and method of forming the same

A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surfaces extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.

Memory cell with buried digit line

The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6 Fis disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3 F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Dram cell design with folded digitline architecture and angled active areas

The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6Fis disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines on a 3F-pitch arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

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Boise, ID, United States of America

Anton P Eppich