Infineon Technologies Austria Ag

Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co. Kg

Other

Anton Mauder

Hans-Joachim Schulze

Franz Hirler

Frank Dieter Pfirsch

Franz-Josef Niedernostheide

Armin Willmeroth

Joachim Weyers

Helmut Strack

Andreas Peter Meiser

Christian Philipp Sandow

Stefan Sedlmaier

Hans Weber

Johannes Georg Laven

Jens Barrenscheen

Roland Rupp

Rudolf Berger

Holger Schulze

Markus Zundel

Ralf Siemieniec

Werner Schustereder

Caspar Leendertz

Wolfgang Lehnert

Francisco Javier Santos Rodriguez

Elmar Falck

Manfred Pfaffenlehner

Johannes Baumgartl

Erich Griebl

Stefan Gamerith

Matteo Dainese

Frank Hille

Hermann Gruber

Reiner Barthelmess

Carsten Schaeffer

Markus Bina

Thoralf Kautzsch

Peter Irsigler

Guenther Ruhl

Hans-Joerg Timme

Uwe Wahl

Markus Schmitt

Roman Knoefler

Oliver Blank

Khalil Hosseini

Martin Gruber

Klemens Pruegl

Oliver Hellmund

Winfried Kaindl

Markus Beninger-Bina

Ralf Otremba

Gerald Deboy

Rolf Weis

Oliver Haeberlen

Wolfgang Werner

Dethard Peters

Carsten Ahrens

Jens Peter Konrath

Michael Bernhard Sommer

Wolfgang Roesner

Michael Hutzler

Rudolf Elpelt

Steffen Bieselt

Alexander Philippou

Hans-Juergen Thees

Sebastian Schmidt

Michael Rueb

Daniel Tutuc

Andreas Voerckel

Joachim Mahler

Edward Fuergut

Jenoe Tihanyi

Till Schloesser

Romain Esteve

Armin Tilke

Stephan Voss

Marko Lemke

Karl Norling

Franz Josef Niedernostheide

Ulrich Glaser

Hubert Rothleitner

Gerald Lackner

Klaus Schiess

Wolfgang Raberg

Stefan Tegen

Manfred Schneegans

Wolfgang Bergner

Christian Jaeger

Gerhard Noebauer

Ingo Muri

Maximilian Roesch

David Laforet

Bernhard Strzalkowski

Thomas Aichinger

Daniel Domes

Adolf Koller

Mark-Matthias Bakran

Friedrich Kroener

Moriz Jelinek

Antonio Vellei

Iris Moder

Olaf Storbeck

A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Power semiconductor device having nanometer-scale structure

A semiconductor device includes a trench structure extending from a first surface into a silicon carbide semiconductor body, the trench structure having a gate electrode that is dielectrically insulated from the semiconductor body, a shielding region adjoining a bottom of the trench structure and forming a first pn junction with a drift structure of the semiconductor body, a body region forming a second pn junction with the drift structure, a source zone arranged between the first surface and the body region and forming a third pn junction with the source zone, wherein a contact portion of the body region extends to the first surface, wherein the source zone surrounds the contact portion of the body region at the first surface, and wherein the trench structure forms an enclosed loop at the first surface that surrounds the source zone and the contact portion of the body region at the first surface.

Method of manufacturing silicon carbide semiconductor devices

A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

Voltage-controlled switching device with channel region

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 mΩ*cm/A.

Voltage-controlled switching device with resistive path

A device includes an interposer including an insulative layer between a lower metal layer and a first upper metal layer and a second upper metal layer, a semiconductor transistor die attached to the first upper metal layer and comprising a first lower main face and a second upper main face, with a drain or collector pad on the first main face and electrically connected to the first upper metal layer, a source or emitter electrode pad and a gate electrode pad on the second main face, a leadframe connected to the interposer and comprising a first lead connected with the first upper metal layer, a second lead connected with the source electrode pad, and a third lead connected with the second upper metal layer, and wherein an electrical connector that is connected between the gate electrode pad and the second upper metal layer is orthogonal to a first electrical connector.

Semiconductor device with improved performance in operation and improved flexibility in the arrangement of power chips

A power diode includes a semiconductor body having an anode region and a drift region, the semiconductor body being coupled to an anode metallization of the power diode and to a cathode metallization of the power diode, and an anode contact zone and an anode damage zone, both implemented in the anode region, the anode contact zone being arranged in contact with the anode metallization, and the anode damage zone being arranged in contact with and below the anode contact zone, wherein fluorine is included within each of the anode contact zone and the anode damage zone at a fluorine concentration of at least 1016 atoms*cm-3.

Power diode and method of manufacturing a power diode

A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.

Single chip power diode and method of producing a single chip power diode

In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Double gate transistor device and method of operating

A power semiconductor device includes: first and second trenches extending from a surface of a semiconductor body along a vertical direction and laterally confining a mesa region along a first lateral direction; source and body regions in the mesa region electrically connected to a first load terminal; and a first insulation layer having a plurality of insulation blocks, two of which laterally confine a contact hole. The first load terminal extends into the contact hole to contact the source and body regions at the mesa region surface. A first insulation block laterally overlaps with the first trench. A second insulation block laterally overlaps with the second trench. The first insulation block has a first lateral concentration profile of a first implantation material of the source region along the first lateral direction that is different from a corresponding second lateral concentration profile for the second insulation block.

Power semiconductor device with p-contact and doped insulation blocks defining contact holes

A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.

Semiconductor component with edge termination region

A method of manufacturing a semiconductor device includes: forming a base portion of a bonding pad on a semiconductor portion, the base portion further comprising a base layer; forming a main surface of the bonding pad, the main surface comprising a bonding region; bonding a bond wire or clip to the bonding region; and forming a supplemental structure directly on the base portion. The supplemental structure laterally adjoins the bond wire or clip or is laterally spaced apart from the bond wire or clip. A volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer.

Method of manufacturing a semiconductor device having a bond wire or clip bonded to a bonding pad

A method for fabricating a semiconductor device includes: forming a trench in a first major surface of a semiconductor body having a first conductivity type; forming a gate in the trench; forming a body region of a second conductivity type in the semiconductor body; implanting a second dopant species into a first region of the body region and a first dopant species into a second region of the body region, the first dopant species providing the first conductivity type, the second dopant species being different from the first dopant species and reducing the diffusion of the first dopant species in the semiconductor body; and thermally annealing the semiconductor body to form a source region that includes the first and second dopant species, and to produce a pn-junction between the source and body regions at a depth dfrom the first major surface, wherein 50 nm&#x3c;d&#x3c;300 nm.

Method for manufacturing a semiconductor device

A silicon carbide device includes a silicon carbide body having a hexagonal crystal lattice with a c-plane and with further main planes. The further main planes include a-planes and m-planes. A mean surface plane of the silicon carbide body is tilted to the c-plane by an off-axis angle. The silicon carbide body includes a columnar portion with column sidewalls. At least three of the column sidewalls are oriented along a respective one of the further main planes. A trench gate structure is in contact with the at least three of the column sidewalls.

Silicon carbide device with trench gate structure and method of manufacturing

A power semiconductor device includes: a semiconductor body with a drift region; a plurality of trenches, wherein two adjacent trenches laterally confine a mesa of the semiconductor body. Each trench extends along a vertical direction and includes a trench electrode, and has a trench width along a first lateral direction and a trench length along a second lateral direction perpendicular to the first lateral direction, the trench length amounting to at least five times the trench width. The device further includes: a semiconductor body region of a second conductivity type in the mesa; a source region in the mesa; an insulation layer above and/or on the source region; a contact plug that extends at least from an upper surface of the insulation layer along the vertical direction so as to contact both the source region and the semiconductor body region.

Mesa contact for a power semiconductor device and method of producing a power semiconductor device

A semiconductor package includes a die pad comprising a die attach surface, a first lead extending away from the die pad, one or more semiconductor dies mounted on the die attach surface, the one or more semiconductor dies comprising first and second bond pads that each face away from the die attach surface, and a distribution element that provides a first transmission path for a first electrical signal between the first lead and the first bond pad of the one or more semiconductor dies and a second transmission path for the first electrical signal between the first lead and the second bond pad of the one or more semiconductor dies. The distribution element comprises at least one integrally formed circuit element that creates a difference in transmission characteristics between the first and second transmission paths.

Semiconductor package with signal distribution element

Growing community of inventors

Kolbermoor, Germany

Anton Mauder