Globalfoundries Inc.

Advanced Micro Devices Corporation

Anthony Mowry

Markus Lenski

Andy C Wei

Andreas Gehring

Casey Scott

David G Farber

Maciej Wiatr

Fred N Hause

Roman Boschke

Vassilios Papageorgiou

Ralf Richter

Frank Wirbeleit

Michael J Austin

John E Moore

Ralf Otterbach

Guido Koerner

Rolf Stephan

Manuj Rathor

Gert Burbach

Markus Forsberg

Thomas Foltyn

Bernhard Trui

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials

A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.

Heat management using power management information

By providing heat dissipation elements or heat pipes in temperature critical areas of a semiconductor device, enhanced performance, reliability and packing density may be achieved. The heat dissipation elements may be formed on the basis of standard manufacturing techniques and may be positioned in close proximity to individual transistor elements and/or may be used for shielding particular circuit portions.

Heat dissipation in temperature critical device areas of semiconductor devices by heat pipes connecting to the substrate backside

By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

Dopant profile tuning for MOS devices by adapting a spacer width prior to implantation

By forming thermocouples in a contact structure of a semiconductor device, respective extension lines of the thermocouples may be routed to any desired location within the die, without consuming valuable semiconductor area in the device layer. Thus, an appropriate network of measurement points of interest may be provided, while at the same time allowing the application of well-established process techniques and materials. Hence, temperature-dependent signals may be obtained from hot spots substantially without being affected by design constraints in the device layer.

Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure

Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures.

Cold temperature control in a semiconductor device

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.

Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

In situ formed drain and source regions in a silicon/germanium containing transistor device

By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements.

Method of forming an interlayer dielectric material having different removal rates during CMP

A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover.

Semiconductor device having a strained semiconductor alloy concentration profile

By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.

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Buda, TX, United States of America

Anthony Mowry