International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundries Singapore Pte. Ltd.

Wispry, Inc.

Smartsens Technology (cayman) Co., Limited

Infineon Technologies Ag

Globalfoundries U.S. 2 LLC

Vanguard International Semiconductor Singapore Pte. Ltd.

Ultratech, Inc.

Elpis Technologies Inc.

Globalfounders Inc.

Anthony K Stamper

Jeffrey P Gambino

Steven M Shank

Zhong-Xiang He

Mark David Jaffe

Vibhor Jain

Christopher Vincent Jahnes

Douglas Duane Coolbaugh

John J Ellis-Monaghan

Edward Crandal Cooney, Iii

Timothy Joseph Dalton

Ebenezer E Eshun

Daniel C Edelstein

Siva P Adusumilli

Stephen Ellinwood Luce

James William Adkisson

Alvin Jose Joseph

John Anthony Fitzsimmons

Eric Jeffrey White

John Joseph Pekarik

Kerry Bernstein

Edmund Juris Sprogis

Hanyi Ding

Robert Mark Rassel

Qizhi Liu

Vincent James McGahay

Arne Watson Ballantine

Andres Bryant

Andrew Herbert Simon

James Stuart Dunn

Mukta G Farooq

Terence B Hook

Robert K Leidy

Timothy Harrison Daubenspeck

Matthew Earl Colburn

William Thomas Motsiff

Thomas M Shaw

Steven H Voldman

Xuefeng Liu

Hyun K Lee

David Louis Harame

Tom C Lee

Brent A Anderson

David V Horak

John Edward Cronin

Jed Hickory Rankin

Sampath Purushothaman

Timothy Dooling Sullivan

Elbert Emin Huang

Wilbur David Pricer

Satyanarayana Venkata Nitta

Fen Chen

Carlos Juan Sambucetti

James Spiros Nakos

Bruce Bennett Doris

Carl John Radens

Yun Yu Wang

Cyril Cabral, Jr

Baozhen Li

Jeffrey Bowman Johnson

Kai D Feng

Rakesh Kumar

Jeffrey W Sleight

Kevin Shawn Petrarca

JunJun Li

John Michael Cotte

Marwan H Khater

Richard Paul Volant

Robert J Gauthier, Jr

Haining S Yang

Jonghae Kim

Ping-Chuan Wang

Soon-Cheon Seo

Wolfgang Sauter

Christopher David Muzzy

Hayden C Cranford, Jr

Paul Stephen Andry

Wai-Kin Li

Souvick Mitra

Eduard Albert Cartier

Tze-Chiang Chen

John Maxwell Cohn

Randy William Mann

Erdem Kaltalioglu

Jason D Hibbeler

Wayne John Howell

Christopher Stephen Putnam

Ruilong Xie

Edward J Nowak

Huilong Zhu

Yusheng Bian

Julien Frougier

Herbert Lei Ho

Julio C Costa

Jagar Singh

Steven J Bentley

Alain F Loiseau

James Albert Slinkman

Richard Quimby Williams

William F Clark, Jr

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

Field effect transistor with shallow trench isolation features within source/drain regions

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Heterojunction bipolar transistor with buried trap rich isolation region

A transistor structure is provided, the structure may be for a high electron mobility transistor (HEMT). The HEMT comprises a channel layer arranged over a substrate, the channel layer may have a top surface. A barrier layer may be arranged over the channel layer. A first opening may be in the barrier layer and extend partially into the channel layer. A first barrier liner may be arranged in the first opening and over the channel layer, the first barrier liner may have a bottom surface. The bottom surface of the first barrier liner may be lower than the top surface of the channel layer.

High electron mobility transistors having barrier liners and integration schemes

Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

Contact-over-active-gate transistor structures with contacts landed on enlarged gate portions

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

Field effect transistor

An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation

An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The isolation structure includes: a polycrystalline isolation layer under the active device, a trench isolation adjacent the active device, and a porous semiconductor layer between the trench isolation and the bulk semiconductor substrate.

IC structure including porous semiconductor layer under trench isolation

The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.

Semiconductor on insulator wafer with cavity structures

According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

Heterojunction bipolar transistors with stress material for improved mobility

The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

Heterojunction bipolar transistor with emitter base junction oxide interface

The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.

Bulk wafer switch isolation

A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

Transistor with air gap under raised source/drain region in bulk semiconductor substrate

Growing community of inventors

Williston, VT, United States of America

Anthony K Stamper