International Business Machines Corporation

Globalfoundries Inc.

Tokyo Electron Limited

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries U.S. 2 LLC

Anthony I Chou

Arvind Kumar

Shreesh Narasimha

Chung-Hsun Lin

Claude Ortolland

Jonathan T Shaw

Toshiharu Furukawa

Renee Tong Mo

Sungjae Lee

Jeffrey W Sleight

Steven J Holmes

Wilfried Haensch

Zhibin Ren

Ashima B Chakravarti

Dinkar Virendra Singh

Fred Buehrer

Judson Robert Holt

Henry K Utomo

Kristen Scheer

Julien Frougier

Robert Russell Robison

Leland Chang

Andrew Mark Greene

Sufi Zafar

Evgeni Petrovich Gousev

Wesley Charles Natzle

Alessandro Cesare Callegari

David L O'Meara

Anthony Dip

Edward P Maciejewski

Cory Wajda

Huiling Shang

Dustin Kenneth Slisher

Ning Su

Qun Gao

Naved Ahmed Siddiqui

Paul J Higgins

Michael Toeller

Toshihara Furukawa

Ruilong Xie

Brent A Anderson

Effendi Leobandung

Veeraraghavan S Basker

Junli Wang

Nicolas J Loubet

Oleg Gluschenkov

Steven M Shank

Terence B Hook

Andres Bryant

Jingyun Zhang

Dominic Joseph Schepis

Michael Patrick Chudzik

James Stuart Dunn

James Spiros Nakos

Christopher Stephen Putnam

Abhishek Dube

Gregory Gower Freeman

Joseph Francis Shepard, Jr

Robert B Laibowitz

BethAnn Rainey

Jay Sanford Burnham

Sagarika Mukesh

Richard Andre Wachnik

Joseph M Lukaitis

Kevin McStay

Christopher M Schnabel

Murshed Mahmud Chowdhury

Paul Daniel Kirsch

Akihisa Sekiguchi

Andrew Gaul

Margaret L Gibson

Wesley C Nazle

Brian M Dufrene

Christopher H Lumbra

Stephen Furkay

Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.

Integration of nanosheets with bottom dielectric isolation and ideal diode

A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs.

Heat pipe for vertically stacked field effect transistors

A semiconductor device is provided. The semiconductor device includes a first field effect device on a first region of a substrate, wherein a first gate structure and an electrostatic discharge device on a second region of the substrate, wherein a second gate structure for the electrostatic discharge device is separated from the substrate by the bottom dielectric layer, and a second source/drain for the electrostatic discharge device is in electrical contact with the substrate, wherein the second source/drain is doped with a second dopant type.

Co-integrated logic, electrostatic discharge, and well contact devices on a substrate

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

Asymmetric high-k dielectric for reducing gate induced drain leakage

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

Semiconductor structure with integrated passive structures

One illustrative method disclosed herein includes, among other things, forming a conformal piezoelectric material liner layer on at least the opposing lateral sidewalls of a fin, forming a recessed layer of insulating material on opposite sides of the fin and on the conformal piezoelectric material liner layer, removing portions of the conformal piezoelectric material liner layer positioned above the recessed layer of insulating material to thereby expose a portion of the fin above the recessed upper surface, and forming a gate structure above the recessed layer of insulating material and around a portion of the fin positioned above the recessed upper surface.

Methods of making FinFET device comprising a piezoelectric liner for generating a surface charge

An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

Asymmetric semiconductor device and method of forming same

Device structures and fabrication methods for an on-chip resistor. A first Seebeck terminal is arranged to overlap with first and second resistor bodies of the on-chip resistor. A second Seebeck terminal is also arranged to overlap with the first and second resistor bodies. The second Seebeck terminal has a spaced relationship with the first Seebeck terminal along a length of the first and second resistor bodies. The temperature coefficient of resistance of the on-chip resistor is based at least in part on a Seebeck coefficient of first and second Seebeck terminals.

On-chip resistors with a tunable temperature coefficient of resistance

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Beacon, NY, United States of America

Anthony I Chou