International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Advanced Micro Devices Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Anthony David Lisi

Lawrence Alfred Clevenger

Maxime Darnon

Satyanarayana Venkata Nitta

Qinghuang Lin

Kaushik Arun Kumar

Satya Venkata Nitta

David V Horak

Daniel C Edelstein

Shom Ponoth

Mukta G Farooq

Wai-Kin Li

Elbert Emin Huang

Richard Stephan Wise

Emily R Kinser

Hermann Wendt

Nicholas C M Fuller

Ravi Prakash Srivastava

Wan-jae Park

Ramona Kei

Hakeem Yusuff

Joseph Edward Linville

Hakeem S B Akinmade-Yusuff

Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Methods for fabrication of an air gap-containing interconnect structure

Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Structures and methods for air gap integration

Air gap-containing interconnect structure having photo-patternable low k material

A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

Three dimensional integration with through silicon vias having multiple diameters

Method for air gap interconnect integration using photo-patternable low k material

A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.

Reversing tone of patterns on integrated circuit and nanoscale fabrication

Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.

Methods of patterning insulating layers using etching techniques that compensate for etch rate variations

Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

Sub-lithographic dimensioned air gap formation and related structure

Process for reversing tone of patterns on integerated circuit and structural process for nanoscale fabrication

Methods for fabricating metal wiring layers of a semiconductor device are provided where damascene interconnect structures are formed in a BEOL process that incorporates a dielectric cap-open-first process to achieve hard mask retention and to control the gouging of a buffer oxide layer to prevent exposure of underlying features protected by the buffer oxide layer.

Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention

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Poughkeepsie, NY, United States of America

Anthony David Lisi