International Business Machines Corporation

Globalfoundries Inc.

International Business Corporation

Anson Jay Call

David John Russell

Vijayeshwar Das Khanna

Krishna R Tunga

Kathleen Ann Stalter

Shaji Farooq

Stephen Anthony DeLaurentis

Sampath Purushothaman

Sung Kwon Kang

Frank Louis Pompeo

Paul Robert Walling

Stephen L Buchwalter

Sushumna Iruvanti

Douglas Oliver Powell

Wolfgang Sauter

Wayne Martin Moreau

David Brian Stone

Krishna Gandhi Sachdev

Jeffrey Allen Zitz

Jean Audet

Peter Jeffrey Brofman

Edmund D Blackshear

Brian W Quinlan

Michael Berger

Jeffrey Thomas Coffin

Karl G Hoebener

Marie S Cole

Francesco Preda

Eric W Tremble

Erwin B Cohen

John R Behun

Dany Minier

Stanley J Jasne

Francis F Cappo

John C Milliken

Bruno T Klingel

Stephen H Meisner

Paul Anthony Zucco

Kamal Kumar Sikka

Roger Donell Weekly

Sudipta Kumar Ray

Shidong Li

Steven Paul Ostrander

Lewis Sigmund Goldmann

Raymond A Jackson

Mukta S Farooq

Mark G Courtney

Jason Lee Frankel

Gregory Blair Martin

Franklin M Baez

Marek Andrzej Orlowski

Rui Wang

Kevin Grosselfinger

Roxan Lemire

Deana Cosmadelis

Gilles Poitras

Frank Louis Pompeo Jr

Alain Ayotte

Frank Louis Pompeo, Jr

Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.

Semiconductor package metal shadowing checks

An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.

Connected plane stiffener within integrated circuit chip carrier

A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

Automated generation of surface-mount package design

An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.

Reduction of laminate failure in integrated circuit (IC) device carrier

Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.

Semiconductor package via stack checking

A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

Split ball grid array pad for multi-chip modules

An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

Method of fabricating contacts of an electronic package structure to reduce solder interconnect stress

A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

Reduction of solder interconnect stress

Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.

Laminate substrate thermal warpage prediction for designing a laminate substrate

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

Copper feature design for warpage control of substrates

A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.

A method of predicting warpage of a laminate is disclosed in which in-plane copper imbalance is calculated. A method of designing an organic build-up laminate is provided in which in-plane copper imbalance is calculated and imbalances are corrected.

In-plane copper imbalance for warpage prediction

An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.

Growing community of inventors

Poughkeepsie, NY, United States of America

Anson Jay Call