Advanced Micro Devices Corporation

Anne E Sanderfer

Minh Van Ngo

Jeffrey Allan Shields

Simon S Chan

King Wai Kelwin Ko

Scott Allan Bell

Lewis N Shen

Che-Hoo Ng

Susan H Chen

Jacques J Bertrand

Christopher Lee Pike

Pei-Yuan Gao

Jiahua Huang

Judi Quan Rizzuto

The present invention relates to a system and a method for reducing the linewidth of ultra thin resist features. The present invention accomplishes this end by applying a densification process to an ultra thin resist having a thickness of less than about 2500 &angst; formed over a semiconductor structure. In one aspect of the present invention, the method includes providing a semiconductor substrate having a device film layer formed thereon. An ultra thin resist is then deposited over the device film layer. The ultra thin resist is patterned according to a desired structure or feature using conventional photolithography techniques. Following development, the ultra thin resist is implanted with a dopant. After the implantation is substantially completed, the device film layer is anisotropically etched.

Method for ultra thin resist linewidth reduction using implantation

A method of manufacturing a semiconductor device by forming layers of materials on a semiconductor substrate and utilizing a series of etch chemistries to remove portions of the layers of materials to form a metal stack. A patterned layer of photoresist determines the portions of the layers that will be etched. An etch process etches a hardmask material, a breakthrough etch process etches an antireflection layer, a conventional main etch process etches approximately 80 percent of the metal film, a first overetch process for a first selected period of time and a second overetch process for a second selected period of time provides a metal film stack having straight profiles and smooth sidewalls.

BC13/AR chemistry for metal overetching on a high density plasma etcher

Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-containing plasma at a temperature of at least about 400&deg; C. and gap filling with a dielectric material, e.g. HDP oxide by HDPCVD.

Method of reducing stress corrosion induced voiding of patterned metal layers

A method of manufacturing semiconductor wafers wherein a metal layer is formed on a surface of a layer of interlayer dielectric on a partially completed semiconductor wafer and if it is determined that the metal layer is faulty, the faulty metal layer is removed, the surface of the layer of interlayer dielectric is lowered below the tops of metal plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized to the surface of the layer of interlayer dielectric and the metal layer is reformed on the surface of the interlayer dielectric. If the metal layer is determined to be good, the metal layer is etched. If the metal etch is faulty, the metal layer is removed, the layer of interlayer dielectric is reduced to below the tops of plugs formed in the layer of interlayer dielectric, the tops of the metal plugs are planarized down to the surface of the layer of interlayer dielectric and the layer of metal is reformed.

Method to rework device with faulty metal stack layer

The inventive method provides a wet cleaning of semiconductor devices on semiconductor wafers after photoresist is stripped. Semiconductor wafers are placed into a centrifuge carriage of a processing chamber. The centrifuge carriage rotates the semiconductor wafers. N-methylpyrrolidine heated to a temperature between 65&deg; C. and 85&deg; C. is sprayed onto the semiconductor wafers. Next N-methylpyrrolidine at room temperature is sprayed onto the semiconductor wafers. Finally, water at room temperature is sprayed onto the semiconductor wafers. The inventive method provides high throughput cleaning without undue corrosion or damage to metal layers.

Minimizing metal corrosion during post metal solvent clean

Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a plasma containing ammonia or ammonia and oxygen at a temperature of at least about 400&deg; C. and gap filling with a dielectric material, e.g. HDP oxide by HDP CVD.

Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers

A defective photoresist mask is removed from a metal layer prior to etching by low-temperature processing to minimize or substantially eliminate any resulting residue on the metal layer, thereby enabling the formation of an interconnection pattern with minimal defects. Embodiments include removing the defective mask by applying a solvent at a temperature of about 80&deg; C. or less, forming a new photoresist mask, and etching the underlying metal layer. The substantial elimination of residue on the metal layer prior to etching avoids bridging between resulting interconnection lines and, hence, short circuiting and device failure.

Low temperature photoresist removal for rework during metal mask formation

A method of manufacturing a semiconductor wafer wherein a layer of hardmask material is formed on the surface of a metal layer formed on a layer of interlayer dielectric formed on a semiconductor substrate on and in which active devices have been formed. A layer of photoresist is formed on the surface of the layer of hardmask material, patterned and developed exposing portions of the underlying layer of hardmask material. The semiconductor wafer is placed in an etched and the layer of hardmask material is etched in a first process utilizing a combination fluorine and chlorine chemistry and the metal layer is etched in a second process utilizing a combination fluorine and chlorine chemistry.

Insitu hardmask and metal etch in a single etcher

A method of manufacturing a semiconductor wafer in a chamber having a chuck and in which temperature changes in the chamber cause residual manufacturing materials to fall onto the surface of a production wafer placed on the chuck. When the temperature of the chamber is to be changed, a protection wafer is placed on the surface of the chuck. When the temperature has been changed, the protection wafer is removed from the surface of the chuck and a production wafer is placed on the surface of the chuck and clamped. When the process is complete the production wafer is removed and the protection wafer is placed on the chuck.

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Campbell, CA, United States of America

Anne E Sanderfer